Nothing Special   »   [go: up one dir, main page]

skip to main content
Skip header Section
Principles of CMOS VLSI design: a systems perspectiveJuly 1985
Publisher:
  • Addison-Wesley Longman Publishing Co., Inc.
  • 75 Arlington Street, Suite 300 Boston, MA
  • United States
ISBN:978-0-201-08222-7
Published:01 July 1985
Pages:
531
Skip Bibliometrics Section
Reflects downloads up to 18 Nov 2024Bibliometrics
Abstract

No abstract available.

Cited By

  1. Han H, Xie K, Wang T, Zhu X, Zhao Y and Xu F (2023). RescQR: Enabling Reliable Data Recovery in Screen-Camera Communication System, IEEE Transactions on Mobile Computing, 23:5, (3510-3522), Online publication date: 1-May-2024.
  2. Li S and Liu J (2023). A novel design of a dependable and fault-tolerant multi-layer banyan network based on a crossbar switch for nano communication, Cluster Computing, 26:2, (1601-1609), Online publication date: 1-Apr-2023.
  3. Verma P, Sharma A, Noor A, Mishra A and Pandey V (2019). A novel approach for noise tolerant energy efficient TSPC dynamic circuit design, Analog Integrated Circuits and Signal Processing, 100:1, (119-131), Online publication date: 1-Jul-2019.
  4. ACM
    Yoon H, Lowe-Power J and Sohi G (2018). Filtering Translation Bandwidth with Virtual Caching, ACM SIGPLAN Notices, 53:2, (113-127), Online publication date: 30-Nov-2018.
  5. Maleknejad M, Mohammadi S, Mirhosseini S, Navi K, Naji H and Hosseinzadeh M (2018). A low-power high-speed hybrid multi-threshold full adder design in CNFET technology, Journal of Computational Electronics, 17:3, (1257-1267), Online publication date: 1-Sep-2018.
  6. ACM
    Yoon H, Lowe-Power J and Sohi G Filtering Translation Bandwidth with Virtual Caching Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, (113-127)
  7. Adapa B, Biswas D, Bhardwaj S, Raghuraman S, Acharyya A and Maharatna K (2017). Coordinate Rotation-Based Low Complexity $K$ -Means Clustering Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25:4, (1568-1572), Online publication date: 1-Apr-2017.
  8. Aghaei B, Khademzadeh A, Reshadi M and Badie K (2017). Link Testing, Journal of Electronic Testing: Theory and Applications, 33:2, (209-225), Online publication date: 1-Apr-2017.
  9. ACM
    Liu Q, Moreto M, Abella J, Cazorla F and Valero M (2016). DReAM, ACM Transactions on Design Automation of Electronic Systems, 22:1, (1-26), Online publication date: 28-Dec-2016.
  10. Safaei Mehrabani Y and Eshghi M (2016). Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24:11, (3268-3281), Online publication date: 1-Nov-2016.
  11. Phatak D and Houston S (2016). New distributed algorithms for fast sign detection in residue number systems (RNS), Journal of Parallel and Distributed Computing, 97:C, (78-95), Online publication date: 1-Nov-2016.
  12. Sharifi F, Panahi A, Sharifi H, Navi K, Bagherzadeh N and Thapliyal H (2016). Design of quaternary 4-2 and 5-2 compressors for nanotechnology, Computers and Electrical Engineering, 56:C, (64-74), Online publication date: 1-Nov-2016.
  13. ACM
    Hussein A, Hosking A, Payer M and Vick C (2015). Don't race the memory bus: taming the GC leadfoot, ACM SIGPLAN Notices, 50:11, (15-27), Online publication date: 28-Jan-2016.
  14. Kahng A, Luo M, Nam G, Nath S, Pan D and Robins G Toward Metrics of Design Automation Research Impact Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, (263-270)
  15. ACM
    Hussein A, Hosking A, Payer M and Vick C Don't race the memory bus: taming the GC leadfoot Proceedings of the 2015 International Symposium on Memory Management, (15-27)
  16. ACM
    Abusultan M and Khatri S Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs Proceedings of the 25th edition on Great Lakes Symposium on VLSI, (111-114)
  17. Lu A, Lu H, Jang E, Lin Y, Hung C, Chuang C and Lin R Simultaneous transistor pairing and placement for CMOS standard cells Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (1647-1652)
  18. Yu L, Saxena S, Hess C, Elfadel I, Antoniadis D and Boning D Statistical library characterization using belief propagation across multiple technology nodes Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (1383-1388)
  19. ACM
    Liu Q, Moreto M, Jimenez V, Abella J, Cazorla F and Valero M (2013). Hardware support for accurate per-task energy metering in multicore systems, ACM Transactions on Architecture and Code Optimization, 10:4, (1-27), Online publication date: 1-Dec-2013.
  20. Lyras G, Rodopoulos D, Papanikolaou A and Soudris D Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems Proceedings of the Conference on Design, Automation and Test in Europe, (655-658)
  21. ACM
    Tai T and Lai Y (2013). Power minimization for dynamically reconfigurable FPGA partitioning, ACM Transactions on Embedded Computing Systems, 12:1s, (1-22), Online publication date: 1-Mar-2013.
  22. ACM
    Kumar M Design of 9-transistor single bit full adder Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology, (337-340)
  23. Wei T, Mishra P, Wu K and Zhou J (2012). Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems, Journal of Systems and Software, 85:6, (1386-1399), Online publication date: 1-Jun-2012.
  24. Wairya S, Nagaria R and Tiwari S (2012). Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design, VLSI Design, 2012, (7-7), Online publication date: 1-Jan-2012.
  25. Khursheed S, Al-Hashimi B, Chakrabarty K and Harrod P (2010). Gate-sizing-based single Vdd test for bridge defects in multivoltage designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:9, (1409-1421), Online publication date: 1-Sep-2010.
  26. ACM
    Liu F, Tan Q, Song X and Abbasi N AOP-based high-level power estimation in SystemC Proceedings of the 20th symposium on Great lakes symposium on VLSI, (353-356)
  27. Kumar N, Katkoori S, Rader L and Vemuri R (1995). Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems, IEEE Design & Test, 12:3, (70-84), Online publication date: 1-May-2010.
  28. ACM
    Saravanan S and Madheswaran M Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique Proceedings of the International Conference and Workshop on Emerging Trends in Technology, (986-990)
  29. ACM
    Lee H and Kim B (2010). Coscheduling of processor voltage and control task period for energy-efficient control systems, ACM Transactions on Embedded Computing Systems, 9:3, (1-24), Online publication date: 1-Feb-2010.
  30. Champac V, Avendaño V and Figueras J (2010). Built-in sensor for signal integrity faults in digital interconnect signals, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18:2, (256-269), Online publication date: 1-Feb-2010.
  31. Balasubramanian P and Mastorakis N A low power gate level full adder module Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals, (246-248)
  32. Chouhan S, Bose R and Balakrishnan M (2009). Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes, IEEE Transactions on Wireless Communications, 8:10, (5348-5355), Online publication date: 1-Oct-2009.
  33. Mohanty S (2009). A secure digital camera architecture for integrated real-time digital rights management, Journal of Systems Architecture: the EUROMICRO Journal, 55:10-12, (468-480), Online publication date: 1-Oct-2009.
  34. Lee J and Ha D (2009). FleXilicon architecture and its VLSI implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:8, (1021-1033), Online publication date: 1-Aug-2009.
  35. ACM
    Inoue K, Kaneko M and Iwagaki T Safe clocking for the setup and hold timing constraints in datapath synthesis Proceedings of the 19th ACM Great Lakes symposium on VLSI, (27-32)
  36. Khursheed S, Al-Hashimi B and Harrod P Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing Proceedings of the Conference on Design, Automation and Test in Europe, (1349-1354)
  37. Lin Y and Hung L (2009). Fast problem-size-independent parallel prefix circuits, Journal of Parallel and Distributed Computing, 69:4, (382-388), Online publication date: 1-Apr-2009.
  38. ACM
    Gulati K, Khatri S and Li P Closed-loop modeling of power and temperature profiles of FPGAs Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (287-287)
  39. ACM
    Lin Y and Hung L (2009). Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2, ACM Transactions on Design Automation of Electronic Systems, 14:1, (1-13), Online publication date: 1-Jan-2009.
  40. ACM
    Romanescu B and Sorin D Core cannibalization architecture Proceedings of the 17th international conference on Parallel architectures and compilation techniques, (43-51)
  41. ACM
    Venkatraman A, Garg R and Khatri S A robust, fast pulsed flip-flop design Proceedings of the 18th ACM Great Lakes symposium on VLSI, (119-122)
  42. King S, Tucek J, Cozzie A, Grier C, Jiang W and Zhou Y Designing and implementing malicious hardware Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats, (1-8)
  43. ACM
    Pandey S and Drechsler R Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs Proceedings of the conference on Design, automation and test in Europe, (206-211)
  44. Chun S, Kim T and Kang S A new low energy BIST using a statistical code Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (647-652)
  45. Pandey S and Drechsler R Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (601-606)
  46. ACM
    Gassend B, Dijk M, Clarke D, Torlak E, Devadas S and Tuyls P (2008). Controlled physical random functions and applications, ACM Transactions on Information and System Security, 10:4, (1-22), Online publication date: 1-Jan-2008.
  47. Singh M and Nowick S (2007). The design of high-performance dynamic asynchronous pipelines, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:11, (1270-1283), Online publication date: 1-Nov-2007.
  48. Bucci M, Giancane L, Luzzi R and Trifiletti A (2007). A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards, IEEE Transactions on Dependable and Secure Computing, 4:4, (245-251), Online publication date: 1-Oct-2007.
  49. ACM
    Xu R, Melhem R and Mossé D A unified practical approach to stochastic DVS scheduling Proceedings of the 7th ACM & IEEE international conference on Embedded software, (37-46)
  50. Li Y, Wang Z, Ruan J and Dai K A low-power globally synchronous locally asynchronous FFT processor Proceedings of the Third international conference on High Performance Computing and Communications, (168-179)
  51. Guerrero D, Millan A, Juan J, Bellido M, Ruiz-de-Clavijo P, Ostua E and Viejo J Static power consumption in CMOS gates using independent bodies Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (404-412)
  52. Li Y, Wang Z, Zhao X, Ruan J and Dai K Design of a low-power embedded processor architecture using asynchronous function units Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture, (354-363)
  53. Lang T and Nannarelli A (2007). A Radix-10 Digit-Recurrence Division Unit, IEEE Transactions on Computers, 56:6, (727-739), Online publication date: 1-Jun-2007.
  54. ACM
    Agrawal P, STG S, Oke A and Vijay S A path based modeling approach for dynamic power estimation Proceedings of the 17th ACM Great Lakes symposium on VLSI, (588-593)
  55. Jejurikar R and Gupta R (2006). Optimized Slowdown in Real-Time Task Systems, IEEE Transactions on Computers, 55:12, (1588-1598), Online publication date: 1-Dec-2006.
  56. Park J and Mooney V (2006). Sleepy stack leakage reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:11, (1250-1263), Online publication date: 1-Nov-2006.
  57. Ghosh S (2006). A predictive dynamic output buffer reconfiguration (PDOBR) architecture for ATM networks, Computer Communications, 29:17, (3609-3624), Online publication date: 1-Nov-2006.
  58. Wu H and Parameswaran S Minimising the energy consumption of real-time tasks with precedence constraints on a single processor Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing, (45-56)
  59. ACM
    Jayakumar N, Garg R, Gamache B and Khatri S A PLA based asynchronous micropipelining approach for subthreshold circuit design Proceedings of the 43rd annual Design Automation Conference, (419-424)
  60. ACM
    Amin C, Kashyap C, Menezes N, Killpack K and Chiprout E A multi-port current source model for multiple-input switching effects in CMOS library cells Proceedings of the 43rd annual Design Automation Conference, (247-252)
  61. Pitkänen T, Mäkinen R, Heikkinen J, Partanen T and Takala J Low-power, high-performance TTA processor for 1024-point fast fourier transform Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation, (227-236)
  62. Tien T, Tsai C, Chang S and Yeh C (2006). Power minimization for dynamic PLAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:6, (616-624), Online publication date: 1-Jun-2006.
  63. Kagaris D and Haniotakis T Transistor-Level Optimization of Supergates Proceedings of the 7th International Symposium on Quality Electronic Design, (682-690)
  64. Gebali F and Rafiq A (2006). Processor Array Architectures for Deep Packet Classification, IEEE Transactions on Parallel and Distributed Systems, 17:3, (241-252), Online publication date: 1-Mar-2006.
  65. Litman A Parceling the butterfly and the batcher sorting network Theoretical Computer Science, (129-142)
  66. Lin Y and Su C (2005). Faster optimal parallel prefix circuits, Journal of Parallel and Distributed Computing, 65:12, (1585-1595), Online publication date: 1-Dec-2005.
  67. Jayakumar N and Khatri S Minimum Energy Near-threshold Network of PLA based Design Proceedings of the 2005 International Conference on Computer Design, (399-404)
  68. Lee S, Nam G, Chae J, Kim H and Drake A (2005). Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13:10, (1167-1178), Online publication date: 1-Oct-2005.
  69. Raja T, Agrawal V and Bushnell M Design of variable input delay gates for low dynamic power circuits Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (436-445)
  70. ACM
    Xu R, Mossé D and Melhem R Minimizing expected energy in real-time embedded systems Proceedings of the 5th ACM international conference on Embedded software, (251-254)
  71. ACM
    Aguirre M and Linares M An alternative logic approach to implement high-speed low-power full adder cells Proceedings of the 18th annual symposium on Integrated circuits and system design, (166-171)
  72. Bhadra J, Martin A and Abraham J (2005). A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor, Formal Methods in System Design, 27:1-2, (67-112), Online publication date: 1-Sep-2005.
  73. ACM
    Hensley J, Singh M and Lastra A A fast, energy-efficient z-comparator Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, (41-44)
  74. ACM
    Gao F and Hayes J Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages Proceedings of the 42nd annual Design Automation Conference, (31-36)
  75. Takahashi O, Cook R, Cottier S, Dhong S, Flachs B, Hirairi K, Kawasumi A, Murakami H, Noro H, Oh H, Onish S, Pille J and Silberman J The circuit design of the synergistic processor element of a CELL processor Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, (111-117)
  76. ACM
    Spjuth M, Karlsson M and Hagersten E Skewed caches from a low-power perspective Proceedings of the 2nd conference on Computing frontiers, (152-160)
  77. Kim C, Hong C and Kwon S (2005). A digit-serial multiplier for finite field GF(2), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13:4, (476-483), Online publication date: 1-Apr-2005.
  78. Nassif S and Li Z A More Effective C_{EFF} Proceedings of the 6th International Symposium on Quality of Electronic Design, (648-653)
  79. Varghese V, Chen T and Young P Systematic Analysis of Active Clock Deskewing Systems Using Control Theory Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, (820-825)
  80. Omana M, Rossi D and Metra C (2005). Low Cost and High Speed Embedded Two-Rail Code Checker, IEEE Transactions on Computers, 54:2, (153-164), Online publication date: 1-Feb-2005.
  81. ACM
    Varghese V, Chen T and Young P Stability analysis of active clock deskewing systems using a control theoretic approach Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (600-605)
  82. ACM
    Agarwal K, Sylvester D, Blaauw D and Devgan A Achieving continuous VT performance in a dual VT process Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (393-398)
  83. ACM
    Zou Y, Zhou Q, Cai Y, Hong X and Tan S Analysis of buffered hybrid structured clock networks Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (93-98)
  84. ACM
    Li J Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (65-70)
  85. Yan Z, Sarwate D and Liu Z (2005). High-speed systolic architectures for finite field inversion, Integration, the VLSI Journal, 38:3, (383-398), Online publication date: 1-Jan-2005.
  86. Bose S (2004). Modeling Custom Digital Circuits for Test, Journal of Electronic Testing: Theory and Applications, 20:6, (591-609), Online publication date: 1-Dec-2004.
  87. Amin C, Dartu F and Ismail Y Modeling unbuffered latches for timing analysis Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (254-260)
  88. Kasnavi A, Wang J, Shahram M and Zejda J Analytical modeling of crosstalk noise waveforms using Weibull function Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (141-146)
  89. ACM
    Xu R, Xi C, Melhem R and Moss D Practical PACE for embedded systems Proceedings of the 4th ACM international conference on Embedded software, (54-63)
  90. ACM
    Mathew B, Davis A and Parker M A low power architecture for embedded perception Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, (46-56)
  91. ACM
    Mamidipaka M, Khouri K, Dutt N and Abadir M Analytical models for leakage power estimation of memory array structures Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (146-151)
  92. ACM
    Mathew B and Davis A A loop accelerator for low power embedded VLIW processors Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (6-11)
  93. Andreev B, Titlebaum E and Friedman E (2004). Complex ±1 Multiplier Based on Signed-Binary Transformations, Journal of VLSI Signal Processing Systems, 38:1, (13-24), Online publication date: 1-Aug-2004.
  94. Sunwoo M and Oh S (2004). A Multiplierless 2-D Convolver Chip for Real-Time Image Processing, Journal of VLSI Signal Processing Systems, 38:1, (63-71), Online publication date: 1-Aug-2004.
  95. ACM
    Coron J, Naccache D and Kocher P (2004). Statistics and secret leakage, ACM Transactions on Embedded Computing Systems, 3:3, (492-508), Online publication date: 1-Aug-2004.
  96. Lorch J and Smith A (2004). PACE, IEEE Transactions on Computers, 53:7, (856-869), Online publication date: 1-Jul-2004.
  97. Iyer B, Srinivasan S and Jacob B Extended Split-Issue Proceedings of the 31st annual international symposium on Computer architecture
  98. ACM
    Wang K and Marek-Sadowska M Buffer sizing for clock power minimization subject to general skew constraints Proceedings of the 41st annual Design Automation Conference, (159-164)
  99. ACM
    Wang K and Marek-Sadowska M Clock network sizing via sequential linear programming with time-domain analysis Proceedings of the 2004 international symposium on Physical design, (182-189)
  100. ACM
    Iyer B, Srinivasan S and Jacob B (2004). Extended Split-Issue, ACM SIGARCH Computer Architecture News, 32:2, (364), Online publication date: 2-Mar-2004.
  101. Porto R and Agostini L Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation Proceedings of the conference on Design, automation and test in Europe - Volume 3
  102. Bhattacharjee S and Pradhan D LPRAM Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (390-393)
  103. Huang H, Wang C and Jou J Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (280-283)
  104. Saponara S, Fanucci L and Terreni P (2004). Design of a low-power VLSI macrocell for nonlinear adaptive video noise reduction, EURASIP Journal on Advances in Signal Processing, 2004, (1921-1930), Online publication date: 1-Jan-2004.
  105. Lin Y and Hsiao J (2004). A new approach to constructing optimal parallel prefix circuits with small depth, Journal of Parallel and Distributed Computing, 64:1, (97-107), Online publication date: 1-Jan-2004.
  106. Paul A, Jeyakumar A, Neelakantan P and Pratheep K Energy recovery strategy for low power CMOS circuits design Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing, (1-5)
  107. Beckmann B and Wood D TLC Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
  108. Thibeault C (2003). On Faster IDDQ Measurements, Journal of Electronic Testing: Theory and Applications, 19:6, (625-635), Online publication date: 1-Dec-2003.
  109. Hashimoto M, Yamada Y and Onodera H Equivalent Waveform Propagation for Static Timing Analysis Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  110. Amin C, Dartu F and Ismail Y Weibull Based Analytical Waveform Model Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  111. Mamidipaka M, Khouri K, Dutt N and Abadir M IDAP Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  112. Yan L, Luo J and Jha N Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  113. ACM
    Suresh D, Agrawal B, Yang J, Najjar W and Bhuyan L Power efficient encoding techniques for off-chip data buses Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, (267-275)
  114. ACM
    Li Z, Lu X, Qiu W, Shi W and Walker D (2003). A circuit level fault model for resistive bridges, ACM Transactions on Design Automation of Electronic Systems, 8:4, (546-559), Online publication date: 1-Oct-2003.
  115. Mamidipaka M, Hirschberg D and Dutt N (2003). Adaptive low-power address encoding techniques using self-organizing lists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:5, (827-834), Online publication date: 1-Oct-2003.
  116. Baumgartner J, Heyman T, Singhal V and Aziz A (2003). An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists, Formal Methods in System Design, 23:1, (39-65), Online publication date: 1-Jul-2003.
  117. McGregor J and Lee R (2003). Architectural techniques for accelerating subword permutations with repetitions, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (325-335), Online publication date: 1-Jun-2003.
  118. Kim C, Kwon S, Kim J and Hong C A compact and fast division architecture for a finite field GF(2m) Proceedings of the 2003 international conference on Computational science and its applications: PartI, (855-864)
  119. ACM
    Lorch J and Smith A Operating System Modifications for Task-Based Speed and Voltage Proceedings of the 1st international conference on Mobile systems, applications and services, (215-229)
  120. ACM
    Yang L and Yuan J A decoupling technique for CMOS strong-coupled structures Proceedings of the 13th ACM Great Lakes symposium on VLSI, (128-131)
  121. ACM
    Natarajan A, Jasinski D, Burleson W and Tessier R A hybrid adiabatic content addressable memory for ultra low-power applications Proceedings of the 13th ACM Great Lakes symposium on VLSI, (72-75)
  122. ACM
    Gassend B, Clarke D, van Dijk M and Devadas S Delay-based circuit authentication and applications Proceedings of the 2003 ACM symposium on Applied computing, (294-301)
  123. Lin Y, Hsu Y and Liu C (2003). Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit, The Journal of Supercomputing, 24:3, (279-304), Online publication date: 1-Mar-2003.
  124. ACM
    Cheng S Arbitrary long digit integer sorter HW/SW co-design Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (538-543)
  125. ACM
    Jeong W and Roy K Robust high-performance low-power carry select adder Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (503-506)
  126. ACM
    Li H, Mak W and Katkoori S Efficient LUT-based FPGA technology mapping for power minimization Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (353-358)
  127. ACM
    Chen J and He L Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (162-167)
  128. Kuang W and Yuan J An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design Proceedings of the 16th International Conference on VLSI Design
  129. Mamidipaka M, Dutt N and Khouri K A Methodology for Accurate Modeling of Energy Dissipation in Array Structures Proceedings of the 16th International Conference on VLSI Design
  130. Chakravarty S Computer circuitry Encyclopedia of Computer Science, (339-348)
  131. ACM
    Chen J and He L Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, (92-97)
  132. ACM
    Gassend B, Clarke D, van Dijk M and Devadas S Silicon physical random functions Proceedings of the 9th ACM conference on Computer and communications security, (148-160)
  133. Jiménez R, Parra P, Sanmartín P and Acosta A (2002). Analysis of High-Performance Flip-Flops for Submicron Mixed-Signal Applications, Analog Integrated Circuits and Signal Processing, 33:2, (145-156), Online publication date: 17-Nov-2002.
  134. ACM
    Ketkar M and Sapatnekar S Standby power optimization via transistor sizing and dual threshold voltage assignment Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (375-378)
  135. ACM
    Xiang H, Chao K and Wong D ECO algorithms for removing overlaps between power rails and signal wires Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (67-74)
  136. ACM
    Worm F, Ienne P, Thiran P and De Micheli G An adaptive low-power transmission scheme for on-chip networks Proceedings of the 15th international symposium on System Synthesis, (92-100)
  137. Amos M, Paun G, Rozenberg G and Salomaa A (2002). Topics in the theory of DNA computing, Theoretical Computer Science, 287:1, (3-38), Online publication date: 25-Sep-2002.
  138. ACM
    Athas W, Youngs L and Reinhart A Compact models for estimating microprocessor frequency and power Proceedings of the 2002 international symposium on Low power electronics and design, (313-318)
  139. Larsson E and Peng Z (2002). An Integrated Framework for the Design and Optimization of SOC Test Solutions, Journal of Electronic Testing: Theory and Applications, 18:4-5, (385-400), Online publication date: 1-Aug-2002.
  140. Messerges T, Dabbish E and Sloan R (2002). Examining Smart-Card Security under the Threat of Power Analysis Attacks, IEEE Transactions on Computers, 51:5, (541-552), Online publication date: 1-May-2002.
  141. Girard P (2002). Survey of Low-Power Testing of VLSI Circuits, IEEE Design & Test, 19:3, (82-92), Online publication date: 1-May-2002.
  142. ACM
    Andreev B, Friedman E and Titlebaum E Efficient implementation of a complex ±1 multiplier Proceedings of the 12th ACM Great Lakes symposium on VLSI, (83-88)
  143. ACM
    Phillips S and Hauck S Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, (165-173)
  144. Oh N, Mitra S and McCluskey E (2002). ED4I, IEEE Transactions on Computers, 51:2, (180-199), Online publication date: 1-Feb-2002.
  145. Bhattacharyya A and Ulman S PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis Proceedings of the 2002 Asia and South Pacific Design Automation Conference
  146. Kim D, Jung J, Lee S, Jeon J and Choi K Behavior-to-placed RTL synthesis with performance-driven placement Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (320-325)
  147. ACM
    Mamidipaka M, Hirschberg D and Dutt N Low power address encoding using self-organizing lists Proceedings of the 2001 international symposium on Low power electronics and design, (188-193)
  148. Weaver C and Austin T A Fault Tolerant Approach to Microprocessor Design Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS), (411-420)
  149. Mukherjee N, Rajski J and Tyszer J (2001). Testing Schemes for FIR Filter Structures, IEEE Transactions on Computers, 50:7, (674-688), Online publication date: 1-Jul-2001.
  150. ACM
    Lee S, Nam G, Chae J, Kim H and Drake A Two-dimensional position deteciton system with MEMS accelerometer for MOUSE applications Proceedings of the 38th annual Design Automation Conference, (852-857)
  151. ACM
    Kim S, Ziesler C and Papaefthymiou M A true single-phase 8-bit adiabatic multiplier Proceedings of the 38th annual Design Automation Conference, (758-763)
  152. ACM
    Mathur A and Saluja S Improved merging of datapath operators using information content and required precision analysis Proceedings of the 38th annual Design Automation Conference, (462-467)
  153. ACM
    Bai G, Bobba S and Hajj I Static timing analysis including power supply noise effect on propagation delay in VLSI circuits Proceedings of the 38th annual Design Automation Conference, (295-300)
  154. ACM
    Folegnani D and González A Energy-effective issue logic Proceedings of the 28th annual international symposium on Computer architecture, (230-239)
  155. Tartagni M, Leone A and Guerrieri R (2001). A Low-Power Block-Matching Cell for VideoCompression, Analog Integrated Circuits and Signal Processing, 27:3, (259-271), Online publication date: 1-Jun-2001.
  156. ACM
    Folegnani D and González A (2001). Energy-effective issue logic, ACM SIGARCH Computer Architecture News, 29:2, (230-239), Online publication date: 1-May-2001.
  157. Nachtergaele L, Catthoor F and Kulkarni C (2001). Random-Access Data Storage Components in Customized Architectures, IEEE Design & Test, 18:3, (40-54), Online publication date: 1-May-2001.
  158. ACM
    Gopalakrishnan P, Odabasioglu A, Pileggi L and Raje S Overcoming wireload model uncertainty during physical design Proceedings of the 2001 international symposium on Physical design, (182-189)
  159. Zenteno A, Champac V and Figueras J (2001). Detectability Conditions of Full Opens in the Interconnections, Journal of Electronic Testing: Theory and Applications, 17:2, (85-95), Online publication date: 1-Apr-2001.
  160. Gao Y and Wong D A graph based algorithm for optimal buffer insertion under accurate delay models Proceedings of the conference on Design, automation and test in Europe, (535-539)
  161. Hashizume M, Ichimiya M, Yotsuyanagi H and Tamesada T CMOS open defect detection by supply current test Proceedings of the conference on Design, automation and test in Europe
  162. ACM
    Huang S An effective low powr design methodology based on interconnect prediction Proceedings of the 2001 international workshop on System-level interconnect prediction, (189-194)
  163. ACM
    Delgado-Frias J and Ratanpal G A VLSI wrapped wave front arbiter for crossbar switches Proceedings of the 11th Great Lakes symposium on VLSI, (85-88)
  164. Um J and Kim T (2001). An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits, IEEE Transactions on Computers, 50:3, (215-233), Online publication date: 1-Mar-2001.
  165. ACM
    Jung S, Baek J and Kim S Short circuit power estimation of static CMOS circuits Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (545-550)
  166. ACM
    Gao Y and Wong D A fast and accurate delay estimation method for buffered interconnects Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (533-538)
  167. ACM
    Lee Y, Lai H and Chen C Optimal spacing and capacitance padding for general clock structures Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (115-119)
  168. ACM
    Butts J and Sohi G A static power model for architects Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, (191-201)
  169. Matthes D and Ford J Technique For Testing A Very High Speed Mixed Signal Read Channel Design Proceedings of the 2000 IEEE International Test Conference
  170. Lin K and Wu C (2000). A Low-Power CAM Design for LZ Data Compression, IEEE Transactions on Computers, 49:10, (1139-1145), Online publication date: 1-Oct-2000.
  171. Wang C and Guo J (2000). New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m), IEEE Transactions on Computers, 49:10, (1120-1125), Online publication date: 1-Oct-2000.
  172. Hasan M and Wassal A (2000). VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor, IEEE Transactions on Computers, 49:10, (1064-1073), Online publication date: 1-Oct-2000.
  173. Gharaybeh M, Agrawal V, Bushnell M and Parodi C (2000). False-Path Removal Using Delay Fault Simulation, Journal of Electronic Testing: Theory and Applications, 16:5, (463-476), Online publication date: 1-Oct-2000.
  174. ACM
    Burd T and Brodersen R Design issues for dynamic voltage scaling Proceedings of the 2000 international symposium on Low power electronics and design, (9-14)
  175. Lin R, Nakano K, Olariu S, Pinotti M, Schwing J and Zomaya A (2000). Scalable Hardware-Algorithms for Binary Prefix Sums, IEEE Transactions on Parallel and Distributed Systems, 11:8, (838-850), Online publication date: 1-Aug-2000.
  176. Yeh W and Jen C (2000). High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, 49:7, (692-701), Online publication date: 1-Jul-2000.
  177. ACM
    Henry D, Kuszmaul B, Loh G and Sami R Circuits for wide-window superscalar processors Proceedings of the 27th annual international symposium on Computer architecture, (236-247)
  178. ACM
    Ye Z, Moshovos A, Hauck S and Banerjee P CHIMAERA Proceedings of the 27th annual international symposium on Computer architecture, (225-235)
  179. ACM
    Attarha A, Nourani M and Lucas C Modeling and simulation of real defects using fuzzy logic Proceedings of the 37th Annual Design Automation Conference, (631-636)
  180. ACM
    Hassoun S Critical path analysis using a dynamically bounded delay model Proceedings of the 37th Annual Design Automation Conference, (260-265)
  181. ACM
    Henry D, Kuszmaul B, Loh G and Sami R (2000). Circuits for wide-window superscalar processors, ACM SIGARCH Computer Architecture News, 28:2, (236-247), Online publication date: 1-May-2000.
  182. ACM
    Ye Z, Moshovos A, Hauck S and Banerjee P (2000). CHIMAERA, ACM SIGARCH Computer Architecture News, 28:2, (225-235), Online publication date: 1-May-2000.
  183. Haniotakis T, Tsiatouhas Y, Nikolos D and Efstathiou C On Testability of Multiple Precharged Domino Logic Proceedings of the 1st International Symposium on Quality of Electronic Design
  184. ACM
    Gristede G and Hwang W A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications Proceedings of the 10th Great Lakes symposium on VLSI, (101-106)
  185. Luo Z and Martonosi M (2000). Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques, IEEE Transactions on Computers, 49:3, (208-218), Online publication date: 1-Mar-2000.
  186. ACM
    Ahmed E and Rose J The effect of LUT and cluster size on deep-submicron FPGA performance and density Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, (3-12)
  187. Shen J and Abraham J (2000). An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation, Journal of Electronic Testing: Theory and Applications, 16:1-2, (67-81), Online publication date: 1-Feb-2000.
  188. ACM
    Wu X, Wei J, Pedram M and Wu Q Low-power design of sequential circuits using a quasi-synchronous derived clock Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (345-350)
  189. ACM
    Pedram M and Wu X Analysis of power-clocked CMOS with application to the design of energy-recovery circuits Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (339-344)
  190. ACM
    Kim T and Um J A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper) Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (313-316)
  191. ACM
    Givargis T, Vahid F and Henkel J A hybrid approach for core-based system-level power modeling Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (141-146)
  192. Lee K, Frieder O and Mak V A parallel VLSI architecture for unformatted data processing Proceedings of the first international symposium on Databases in parallel and distributed systems, (80-86)
  193. ACM
    Anghel L and Nicolaidis M Cost reduction and evaluation of temporary faults detecting technique Proceedings of the conference on Design, automation and test in Europe, (591-598)
  194. ACM
    Gao Y and Wong D Wire-sizing for delay minimization and ringing control using transmission line model Proceedings of the conference on Design, automation and test in Europe, (512-516)
  195. ACM
    Ringe M, Lindenkreuz T and Barke E Static timing analysis taking crosstallk into account Proceedings of the conference on Design, automation and test in Europe, (451-457)
  196. ACM
    Scholl C and Becker B On the generation of multiplexer circuits for pass transistor logic Proceedings of the conference on Design, automation and test in Europe, (372-379)
  197. Austin T DIVA Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, (196-207)
  198. Um J, Kim T and Liu C Optimal allocation of carry-save-adders in arithmetic optimization Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (410-413)
  199. Sinha A, Gupta S and Breuer M Validation and test generation for oscillatory noise in VLSI interconnects Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (289-296)
  200. Givargis T, Henkel J and Vahid F Interface and cache power exploration for core-based embedded system design Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (270-273)
  201. Paar C, Fleischmann P and Soria-Rodriguez P (1999). Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents, IEEE Transactions on Computers, 48:10, (1025-1034), Online publication date: 1-Oct-1999.
  202. Abraham J Position Statement Proceedings of the 1999 IEEE International Test Conference
  203. Gizopoulos D, Paschalis A and Zorian Y (1999). An Effective Built-In Self-Test Scheme for Parallel Multipliers, IEEE Transactions on Computers, 48:9, (936-950), Online publication date: 1-Sep-1999.
  204. ACM
    Meier P, Rutenbar R and Carley L Inverse polarity techniques for high-speed/low-power multipliers Proceedings of the 1999 international symposium on Low power electronics and design, (264-266)
  205. ACM
    Ramprasad S, Hajj I and Najm F An optimization technique for dual-output domino logic Proceedings of the 1999 international symposium on Low power electronics and design, (258-260)
  206. ACM
    Martin T and Siewiorek D The impact of battery capacity and memory bandwidth on CPU speed-setting Proceedings of the 1999 international symposium on Low power electronics and design, (200-205)
  207. ACM
    Sundararajan V and Parhi K Low power synthesis of dual threshold voltage CMOS VLSI circuits Proceedings of the 1999 international symposium on Low power electronics and design, (139-144)
  208. ACM
    Fahim A and Elmasry M SC2L Proceedings of the 1999 international symposium on Low power electronics and design, (88-90)
  209. ACM
    Ramasubramanian B, Schmit H and Carley L Mixed-swing quadrail for low power dual-rail domino logic Proceedings of the 1999 international symposium on Low power electronics and design, (82-84)
  210. ACM
    Balamurugan G and Shanbhag N Energy-efficient dynamic circuit design in the presence of crosstalk noise Proceedings of the 1999 international symposium on Low power electronics and design, (24-29)
  211. Mu F and Svensson C (1999). Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems, IEEE Transactions on Parallel and Distributed Systems, 10:8, (769-780), Online publication date: 1-Aug-1999.
  212. Nicolaidis M and Duarte R (1999). Fault-Secure Parity Prediction Booth Multipliers, IEEE Design & Test, 16:3, (90-101), Online publication date: 1-Jul-1999.
  213. Hansen M, Yalcin H and Hayes J (1999). Unveiling the ISCAS-85 Benchmarks, IEEE Design & Test, 16:3, (72-80), Online publication date: 1-Jul-1999.
  214. Lin Y and Shih C (1999). A New Class of Depth-Size Optimal Parallel Prefix Circuits, The Journal of Supercomputing, 14:1, (39-52), Online publication date: 1-Jul-1999.
  215. ACM
    Wei L, Chen Z, Roy K, Ye Y and De V Mixed-V (MVT) CMOS circuit design methodology for low power applications Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (430-435)
  216. ACM
    Patra P and Narayanan U Automated phase assignment for the synthesis of low power domino circuits Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (379-384)
  217. Kömmerling O and Kuhn M Design principles for tamper-resistant smartcard processors Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology, (2-2)
  218. Bermak A and Austin J VLSI Implementation of a Binary Neural Network-Two Case Studies Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
  219. Chai S, Gentile A and Wills D Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
  220. Tzartzanis N and Athas W Clock-Powered CMOS Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
  221. ACM
    Marquardt A, Betz V and Rose J Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, (37-46)
  222. Khan A, Deval A and Akers L (1999). A Locally Adaptive Multimode Photodetector Circuit, Analog Integrated Circuits and Signal Processing, 18:2-3, (255-275), Online publication date: 1-Feb-1999.
  223. ACM
    Moran D, Dooling D, Wilkins T and Williams R Integrated manufacturing and development (IMaD) Proceedings of the 1999 ACM/IEEE conference on Supercomputing, (9-es)
  224. ACM
    Dick R and Jha N MOCSYN Proceedings of the conference on Design, automation and test in Europe, (55-es)
  225. Nannarelli A and Lang T (1999). Low-Power Divider, IEEE Transactions on Computers, 48:1, (2-14), Online publication date: 1-Jan-1999.
  226. ACM
    Ferrandi F, Macii A, Macii E, Poncino M, Scarsi R and Somenzi F Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (235-241)
  227. ACM
    Narayanan U, Pan P and Liu C Low power logic synthesis under a general delay model Proceedings of the 1998 international symposium on Low power electronics and design, (209-214)
  228. Godambe N and Shi C (1998). Behavioral Level Noise Modeling and Jitter Simulation ofPhase-Locked Loops with Faults Using VHDL-AMS, Journal of Electronic Testing: Theory and Applications, 13:1, (7-17), Online publication date: 1-Aug-1998.
  229. ACM
    López D, Llosa J, Valero M and Ayguadé E Resource widening versus replication Proceedings of the 12th international conference on Supercomputing, (441-448)
  230. Perkins A, Zwolinski M, Chalk C and Wilkins B (1998). Fault Modeling and Simulation Using VHDL-AMS, Analog Integrated Circuits and Signal Processing, 16:2, (141-155), Online publication date: 1-Jun-1998.
  231. ACM
    Kim V and Banerjee P Parallel algorithms for power estimation Proceedings of the 35th annual Design Automation Conference, (672-677)
  232. ACM
    Kao J, Narendra S and Chandrakasan A MTCMOS hierarchical sizing based on mutual exclusive discharge patterns Proceedings of the 35th annual Design Automation Conference, (495-500)
  233. ACM
    Kim T, Jao W and Tjiang S Arithmetic optimization using carry-save-adders Proceedings of the 35th annual Design Automation Conference, (433-438)
  234. ACM
    Ienne P and Grießing A Practical experiences with standard-cell based datapath design tools Proceedings of the 35th annual Design Automation Conference, (396-401)
  235. ACM
    Lakshminarayana G and Jha N FACT Proceedings of the 35th annual Design Automation Conference, (102-107)
  236. Phatak D (1998). Double Step Branching CORDIC, IEEE Transactions on Computers, 47:5, (587-602), Online publication date: 1-May-1998.
  237. Llosa J, Ayguadé E and Valero M (1998). Quantitative Evaluation of Register Pressure on Software Pipelined Loops, International Journal of Parallel Programming, 26:2, (121-142), Online publication date: 1-Apr-1998.
  238. ACM
    Anderson J and Brown S An LPGA with foldable PLA-style logic blocks Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, (244-252)
  239. ACM
    Anderson J, Sheth S and Roy K A coarse-grained FPGA architecture for high-performance FIR filtering Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, (234-244)
  240. Antelo E, Bóo M, Bruguera J and Zapata E (1998). A novel design of a two operand normalization circuit, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6:1, (173-176), Online publication date: 1-Mar-1998.
  241. Bisdounis L, Nikolaidis S, Koufopavlou O and Goutis C Switching response modeling of the CMOS inverter for sub-micron devices Proceedings of the conference on Design, automation and test in Europe, (729-737)
  242. Wang S and Gupta S (1998). ATPG for Heat Dissipation Minimization During Test Application, IEEE Transactions on Computers, 47:2, (256-262), Online publication date: 1-Feb-1998.
  243. Duarte R, Nicolaidis M, Bederr H and Zorian Y (1998). Efficient Totally Self-Checking Shifter Design, Journal of Electronic Testing: Theory and Applications, 12:1-2, (29-39), Online publication date: 1-Feb-1998.
  244. Xing S and Yu W (1998). FPGA Adders, IEEE Design & Test, 15:1, (24-29), Online publication date: 1-Jan-1998.
  245. Narayanan U and Liu C Low power logic synthesis for XOR based circuits Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (570-574)
  246. Cong J, Pan Z, He L, Koh C and Khoo K Interconnect design for deep submicron ICs Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (478-485)
  247. Sivaraman M and Strojwas A Timing analysis based on primitive path delay fault identification Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (182-189)
  248. Raina R, Njinda C and Molyneaux R How Seriously Do You Take Possible-Detect Faults? Proceedings of the 1997 IEEE International Test Conference
  249. Brauch J and Fleischman J DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500 Proceedings of the 1997 IEEE International Test Conference
  250. Miura Y AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS Proceedings of the 1997 IEEE International Test Conference
  251. Wang H, Sun T and Yang Q (1997). Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags, IEEE Transactions on Computers, 46:11, (1187-1201), Online publication date: 1-Nov-1997.
  252. Shi C, Vannelli A and Vlach J (1997). Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning, Journal of Heuristics, 3:3, (225-243), Online publication date: 1-Nov-1997.
  253. ACM
    Lorenz D (1997). Tiling design patterns—a case study using the interpreter pattern, ACM SIGPLAN Notices, 32:10, (206-217), Online publication date: 9-Oct-1997.
  254. ACM
    Lorenz D Tiling design patterns—a case study using the interpreter pattern Proceedings of the 12th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (206-217)
  255. Vinnakota B (1997). Monitoring Power Dissipation for Fault Detection, Journal of Electronic Testing: Theory and Applications, 11:2, (173-181), Online publication date: 1-Oct-1997.
  256. Juan-Chico J, Bellido M, Acosta A, Valencia M and Huertas J (1997). Analysis of Metastable Operation in a CMOS Dynamic D-Latch, Analog Integrated Circuits and Signal Processing, 14:1-2, (143-157), Online publication date: 1-Sep-1997.
  257. ACM
    Girard P, Landrault C, Pravossoudovitch S and Severac D A gate resizing technique for high reduction in power consumption Proceedings of the 1997 international symposium on Low power electronics and design, (281-286)
  258. ACM
    Azam M, Franzon P and Liu W Low power data processing by elimination of redundant computations Proceedings of the 1997 international symposium on Low power electronics and design, (259-264)
  259. ACM
    Goel M and Shanbhag N Dynamic algorithm transformation (DAT) for low-power adaptive signal processing Proceedings of the 1997 international symposium on Low power electronics and design, (161-166)
  260. ACM
    Kamble M and Ghose K Analytical energy dissipation models for low-power caches Proceedings of the 1997 international symposium on Low power electronics and design, (143-148)
  261. ACM
    Kim B, Chung D and Kim L A new 4-2 adder and booth selector for low power MAC unit Proceedings of the 1997 international symposium on Low power electronics and design, (100-103)
  262. ACM
    Nicol C and Larsson P Low power multiplication for FIR filters Proceedings of the 1997 international symposium on Low power electronics and design, (76-79)
  263. ACM
    de Angel E and Swartzlander E Survey of low power techniques for ROMs Proceedings of the 1997 international symposium on Low power electronics and design, (7-11)
  264. ACM
    López D, Valero M, Llosa J and Ayguadé E Increasing memory bandwidth with wide buses Proceedings of the 11th international conference on Supercomputing, (12-19)
  265. Segars S (1997). ARM7TDMI Power Consumption, IEEE Micro, 17:4, (12-19), Online publication date: 1-Jul-1997.
  266. ACM
    Forzan C, Franzini B and Guardiani C Accurate and efficient macromodel of submicron digital standard cells Proceedings of the 34th annual Design Automation Conference, (633-637)
  267. ACM
    Kao J, Chandrakasan A and Antoniadis D Transistor sizing issues and tool for multi-threshold CMOS technology Proceedings of the 34th annual Design Automation Conference, (409-414)
  268. ACM
    Pandey M, Raimi R, Bryant R and Abadir M Formal verification of content addressable memories using symbolic trajectory evaluation Proceedings of the 34th annual Design Automation Conference, (167-172)
  269. ACM
    Dartu F and Pileggi L Calculating worst-case gate delays due to dominant capacitance coupling Proceedings of the 34th annual Design Automation Conference, (46-51)
  270. ACM
    Palacharla S, Jouppi N and Smith J Complexity-effective superscalar processors Proceedings of the 24th annual international symposium on Computer architecture, (206-218)
  271. Miura K, Nakamae K and Fujioka H (1997). Hierarchical VLSI Fault Tracing by Successive CircuitExtraction from CAD Layout Data in the CAD-Linked EB TestSystem, Journal of Electronic Testing: Theory and Applications, 10:3, (255-269), Online publication date: 1-Jun-1997.
  272. Paar C and Soria-Rodriguez P Fast arithmetic architectures for public-key algorithms over Galois fields GF((2n)m) Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques, (363-378)
  273. ACM
    Palacharla S, Jouppi N and Smith J (1997). Complexity-effective superscalar processors, ACM SIGARCH Computer Architecture News, 25:2, (206-218), Online publication date: 1-May-1997.
  274. Godambe N and Shi C Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS Proceedings of the 15th IEEE VLSI Test Symposium
  275. Chang Y, Gupta S and Breuer M Analysis of Ground Bounce in Deep Sub-Micron Circuits Proceedings of the 15th IEEE VLSI Test Symposium
  276. ACM
    Zhou D and Liu X Minimization of chip size and power consumption of high-speed VLSI buffers Proceedings of the 1997 international symposium on Physical design, (186-191)
  277. ACM
    Burns J and Feldman J C5M—a control logic layout synthesis system for high-performance microprocessors Proceedings of the 1997 international symposium on Physical design, (110-115)
  278. Ku H and Hayes J (1997). Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses, IEEE Transactions on Computers, 46:4, (439-455), Online publication date: 1-Apr-1997.
  279. Kundu S and Ghoshal U Inductance Analysis of On-Chip Interconnects Proceedings of the 1997 European conference on Design and Test
  280. Fishburn J Shaping a VLSI Wire to Minimize Elmore Delay Proceedings of the 1997 European conference on Design and Test
  281. Lin R Shift Switching with Domino Logic Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
  282. Eshraghian K, Montiel-Nelson J and Nooshabadi S An Asynchronous Morphological Processor for Multi-Media Applications Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
  283. Agrawal V Low-Power Design by Hazard Filtering Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
  284. Sibai F and Kulkarni S (1997). A Time-Multiplexed Reconfigurable Neuroprocessor, IEEE Micro, 17:1, (58-65), Online publication date: 1-Jan-1997.
  285. Pradhan D, Chatterjee M, Swarna M and Kunz W Gate-level synthesis for low-power using new transformations Proceedings of the 1996 international symposium on Low power electronics and design, (297-300)
  286. Cong J, Koh C and Leung K Simultaneous buffer and wire sizing for performance and power optimization Proceedings of the 1996 international symposium on Low power electronics and design, (271-276)
  287. Acken K, Irwin M and Owens R Power comparisons for barrel shifters Proceedings of the 1996 international symposium on Low power electronics and design, (209-212)
  288. Nannarelli A and Lang T Low-power radix-4 divider Proceedings of the 1996 international symposium on Low power electronics and design, (205-208)
  289. Lu P, Ji J, Chuang C, Wagner L, Hsieh C, Kuang J, Hsu L, Pelella M, Chu S and Anderson C Floating body effects in partially-depleted SOI CMOS circuits Proceedings of the 1996 international symposium on Low power electronics and design, (139-144)
  290. Ishihara T and Yasuura H Basic experimentation on accuracy of power estimation for CMOS VLSI circuits Proceedings of the 1996 international symposium on Low power electronics and design, (117-120)
  291. Miura Y (1996). Real-Time Current Testing for A/D Converters, IEEE Design & Test, 13:2, (34-41), Online publication date: 1-Jun-1996.
  292. ACM
    Austin T and Sohi G High-bandwidth address translation for multiple-issue processors Proceedings of the 23rd annual international symposium on Computer architecture, (158-167)
  293. ACM
    Austin T and Sohi G (1996). High-bandwidth address translation for multiple-issue processors, ACM SIGARCH Computer Architecture News, 24:2, (158-167), Online publication date: 1-May-1996.
  294. Baba-ali A and Farah A An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI Proceedings of the 1996 European conference on Design and Test
  295. Turgis S, Azemard N and Auvergne D Design and selection of buffers for minimum power-delay product Proceedings of the 1996 European conference on Design and Test
  296. Caufape S and Figueras J Power Optimization of Delay Constrained CMOS Bus Drivers Proceedings of the 1996 European conference on Design and Test
  297. Velasco A, Marin X, Carrabina J and Llopis R A Combined Pairing and Chaining Algorithm for CMOS Layout Generation Proceedings of the 1996 European conference on Design and Test
  298. ACM
    Concepcion A and Millican D (1996). Developing the VLSI laboratory for the computer architecture course, ACM SIGCSE Bulletin, 28:1, (47-52), Online publication date: 1-Mar-1996.
  299. ACM
    Concepcion A and Millican D Developing the VLSI laboratory for the computer architecture course Proceedings of the twenty-seventh SIGCSE technical symposium on Computer science education, (47-52)
  300. Kantabutra V (1996). On Hardware for Computing Exponential and Trigonometric Functions, IEEE Transactions on Computers, 45:3, (328-339), Online publication date: 1-Mar-1996.
  301. Agrawal P, Narendran B and Shivakumar N Multi-way partitioning of VLSI circuits Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
  302. Pileggi L Coping with RC(L) interconnect design headaches Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (246-253)
  303. Lillis J, Cheng C and Lin T Optimal wire sizing and buffer insertion for low power and a generalized delay model Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (138-143)
  304. Singh K and Subrahmanyam P Extracting RTL models from transistor netlists Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (11-17)
  305. Kission P, Ding H and Jerraya A VHDL based design methodology for hierarchy and component re-use Proceedings of the conference on European design automation, (470-475)
  306. Pierzynska A and Pilarski S Quality considerations in delay fault testing Proceedings of the conference on European design automation, (196-201)
  307. Paschalis A, Haniotakis T and Nikolos D (1995). Efficient Totally Self-Checking Checkers for a Class of Borden Codes, IEEE Transactions on Computers, 44:11, (1318-1322), Online publication date: 1-Nov-1995.
  308. ACM
    Katevenis M, Vatsolaki P and Efthymiou A (1995). Pipelined memory shared buffer for VLSI switches, ACM SIGCOMM Computer Communication Review, 25:4, (39-48), Online publication date: 1-Oct-1995.
  309. ACM
    Katevenis M, Vatsolaki P and Efthymiou A Pipelined memory shared buffer for VLSI switches Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication, (39-48)
  310. Taylor F and Smith J (1995). A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications, IEEE Transactions on Computers, 44:9, (1121-1130), Online publication date: 1-Sep-1995.
  311. ACM
    Wang H, Sun T and Yang Q CAT—caching address tags Proceedings of the 22nd annual international symposium on Computer architecture, (381-390)
  312. ACM
    Wang H, Sun T and Yang Q (1995). CAT—caching address tags, ACM SIGARCH Computer Architecture News, 23:2, (381-390), Online publication date: 1-May-1995.
  313. ACM
    Chung J, Kao D, Cheng C and Lin T Optimization of power dissipation and skew sensitivity in clock buffer synthesis Proceedings of the 1995 international symposium on Low power design, (179-184)
  314. ACM
    Chren W Low delay-power product CMOS design using one-hot residue coding Proceedings of the 1995 international symposium on Low power design, (145-150)
  315. ACM
    Musoll E and Cortadella J High-level synthesis techniques for reducing the activity of functional units Proceedings of the 1995 international symposium on Low power design, (99-104)
  316. ACM
    Papachristou C, Spining M and Nourani M A multiple clocking scheme for low power RTL design Proceedings of the 1995 international symposium on Low power design, (27-32)
  317. Cong J and Koh C Simultaneous driver and wire sizing for performance and power optimization Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (206-212)
  318. Benini L, Siegel P and De Micheli G (1994). Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, 11:4, (32-41), Online publication date: 1-Oct-1994.
  319. Gary S, Ippolito P, Gerosa G, Dietz C, Eno J and Sanchez H (1994). PowerPC 603, A Microprocessor for Portable Computers, IEEE Design & Test, 11:4, (14-23), Online publication date: 1-Oct-1994.
  320. Phatak D and Koren I (1994). Hybrid Signed-Digit Number Systems, IEEE Transactions on Computers, 43:8, (880-891), Online publication date: 1-Aug-1994.
  321. ACM
    Dartu F, Menezes N, Qian J and Pillage L A gate-delay model for high-speed CMOS circuits Proceedings of the 31st annual Design Automation Conference, (576-580)
  322. ACM
    Maly W Cost of silicon viewed from VLSI design perspective Proceedings of the 31st annual Design Automation Conference, (135-142)
  323. Wolfe A and Boleyn R Two-ported cache alternatives for superscalar processors Proceedings of the 26th annual international symposium on Microarchitecture, (41-48)
  324. Du D, Lin I and Chang K (1993). On Wafer-Packing Problems, IEEE Transactions on Computers, 42:11, (1382-1388), Online publication date: 1-Nov-1993.
  325. ACM
    Hamada T, Cheng C and Chau P Prime Proceedings of the 30th international Design Automation Conference, (531-536)
  326. ACM
    Tiwari V, Ashar P and Malik S Technology mapping for lower power Proceedings of the 30th international Design Automation Conference, (74-79)
  327. Lapointe M, Huynh H and Fortier P (1993). Systematic Design of Pipelined Recursive Filters, IEEE Transactions on Computers, 42:4, (413-426), Online publication date: 1-Apr-1993.
  328. Jha N (1993). Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers, IEEE Transactions on Computers, 42:2, (179-189), Online publication date: 1-Feb-1993.
  329. Chandrakasan A, Potkonjak M, Rabaey J and Brodersen R HYPER-LP Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, (300-303)
  330. Damiani M and De Micheli G Recurrence equations and the optimization of synchronous logic circuits Proceedings of the 29th ACM/IEEE Design Automation Conference, (556-561)
  331. Afghahi M and Svensson C (1992). Performance of Synchronous and Asynchronous Schemes for VLSI Systems, IEEE Transactions on Computers, 41:7, (858-872), Online publication date: 1-Jul-1992.
  332. Levy P (1991). Designing in Power-Down Test Circuits, IEEE Design & Test, 8:3, (31-35), Online publication date: 1-Jul-1991.
  333. Smith D and Lin J (1991). The Tree-Match Chip, IEEE Transactions on Computers, 40:5, (629-639), Online publication date: 1-May-1991.
  334. ACM
    Hill D and Preas B Benchmarks for cell synthesis Proceedings of the 27th ACM/IEEE Design Automation Conference, (317-320)
  335. ACM
    Lin I and Du D Performance-driven constructive placement Proceedings of the 27th ACM/IEEE Design Automation Conference, (103-106)
  336. ACM
    Mak V, Lee K and Frieder O (1991). Exploiting parallelism in pattern matching, ACM Transactions on Information Systems, 9:1, (52-74), Online publication date: 3-Jan-1991.
  337. Dutt N and Gajski D (1990). Design Synthesis and Silicon Compilation, IEEE Design & Test, 7:6, (8-23), Online publication date: 1-Nov-1990.
  338. ACM
    Battelini J and Isukapalli S A special purpose finite element architecture Proceedings of the 28th annual ACM Southeast Regional Conference, (267-273)
  339. Kolla R A dynamic programming approach to the power supply net sizing problem Proceedings of the conference on European design automation, (600-604)
  340. Hinsberger U and Kolla R Cell based performance optimization of combinational circuits Proceedings of the conference on European design automation, (594-599)
  341. Eisele V, Hoppe B and Kiehl O Transmission gate delay models for circuit optimization Proceedings of the conference on European design automation, (558-562)
  342. Wei S, Leroy J and Crappe R An efficient two-dimensional compaction algorithm for VLSI symbolic layout Proceedings of the conference on European design automation, (196-200)
  343. ACM
    Anido M, Allerton D and Zaluska E (1989). A three-port/three-access register file for concurrent processing and I/O communication in a RISC-like graphics engine, ACM SIGARCH Computer Architecture News, 17:3, (354-361), Online publication date: 1-Jun-1989.
  344. ACM
    Rajsuman R, Jayasumana A and Malaiya Y CMOS stuck-open fault detection using single test patterns Proceedings of the 26th ACM/IEEE Design Automation Conference, (714-717)
  345. ACM
    Bamji C and Allen J GRASP: a grammar-based schematic parser Proceedings of the 26th ACM/IEEE Design Automation Conference, (448-453)
  346. ACM
    Prasitjutrakul S and Kubitz W Path-delay constrained floorplanning: a mathematical programming approach for initial placement Proceedings of the 26th ACM/IEEE Design Automation Conference, (364-369)
  347. ACM
    Anido M, Allerton D and Zaluska E A three-port/three-access register file for concurrent processing and I/O communication in a RISC-like graphics engine Proceedings of the 16th annual international symposium on Computer architecture, (354-361)
  348. Molyneaux R and Albicki A (1989). Comments on 'Ternary Scan Design for VLSI Testability' by M. Hu and K.C. Smith, IEEE Transactions on Computers, 38:2, (256-263), Online publication date: 1-Feb-1989.
  349. Jarwala N and Pradhan D (1988). TRAM, IEEE Transactions on Computers, 37:10, (1235-1250), Online publication date: 1-Oct-1988.
  350. Pradhan D and Kamath N RTRAM Proceedings of the 1988 international conference on Test: new frontiers in testing, (263-278)
  351. Cerny E, Aboulhamid E, Bois G and Cloutier J (1988). Built-In Self-Test of a CMOS ALU, IEEE Design & Test, 5:4, (38-48), Online publication date: 1-Jul-1988.
  352. Eickenmeyer R and Patel J Performance evaluation of on-chip register and cache organizations Proceedings of the 15th Annual International Symposium on Computer architecture, (64-72)
  353. Motohara A, Murakami M, Urano M, Masuda Y and Sugano M An approach to fast hierarchical fault simulation Proceedings of the 25th ACM/IEEE Design Automation Conference, (698-703)
  354. Obermeier F and Katz R An electrical optimizer that considers physical layout Proceedings of the 25th ACM/IEEE Design Automation Conference, (453-459)
  355. Baltus D and Allen J SOLO Proceedings of the 25th ACM/IEEE Design Automation Conference, (445-452)
  356. ACM
    Eickenmeyer R and Patel J (1988). Performance evaluation of on-chip register and cache organizations, ACM SIGARCH Computer Architecture News, 16:2, (64-72), Online publication date: 17-May-1988.
  357. ACM
    Salama R, Liu W and Gyurcsik R Software experience with concurrent C and LISP in a distributed system Proceedings of the 1988 ACM sixteenth annual conference on Computer science, (329-334)
  358. ACM
    Wu C, Wojcik A and Ni L A rule-based circuit representation for automated CMOS design and verification Proceedings of the 24th ACM/IEEE Design Automation Conference, (786-792)
  359. ACM
    Subrahmanyam P LCS—a leaf cell synthesizer employing formal deduction techniques Proceedings of the 24th ACM/IEEE Design Automation Conference, (459-465)
  360. Guyot A, Hochet B and Muller J (1987). A Way to Build Efficient Carry-Skip Adders, IEEE Transactions on Computers, 36:10, (1144-1152), Online publication date: 1-Oct-1987.
  361. Kaneko H, Miki Y, Nohara S, Koya K and Araki M A 32-bit CMOS microprocessor with six-stage pipeline structure Proceedings of 1986 ACM Fall joint computer conference, (1000-1007)
  362. Kahng A, Luo M, Nam G, Nath S, Pan D and Robins G Toward metrics of design automation research impact 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (263-270)
Contributors
  • Macquarie University
  • Chungbuk National University

Reviews

Albert Alkins Mullin

Recall that Very Large Scale Integrated (VLSI) systems pervade many of the products of the cybernetic marketplace, e.g., advanced computers, high-speed communication systems, and super industrial controllers. Further, VLSI systems and their sister systems, the Very High Speed Integrated (VHSI) systems, are indispensible for solutions to the pressing command, control, and communications problems of the modern cybernetic battlefield, among other problem areas. Indeed, VLSI and VHSI systems are expected to contribute significantly to the performance of ultra-complex signal processing, data processing, sensors, and communications requirements for the emerging “Star Wars” efforts. Here is an outstanding introductory textbook and research reference on the engineering foundations of integrated systems design, working in the VLSI medium of Complementary Metal-Oxide Semiconductor (CMOS) technology. The authors' approach is an evolution from the approach used in the earlier classical work on VLSI systems by Mead and Conway [1], where significant emphasis was given to nMOS technology. In recent years, there has been a major shift in the technological medium used for the design of high complexity and high speed digital microelectronics from nMOS to CMOS. The authors give no special emphasis to the physics of VLSI design or to structured VLSI design. On the other hand, the book clarifies the similarities and differences among various CMOS processes and their influences on system design. In order to keep the level of technical expertise high, several of the sections (e.g., system case studies) were written by the authors' colleagues. Indeed, the authors could even be called editors. Further, the value of the book is enhanced by the inclusion of several multicolored plates depicting various processes, structures, layouts, and design aids. The nine chapters include such basic topics as: (1)an introduction to CMOS circuits; (2)MOS transistor theory; (3)CMOS processing technology; (4)circuit characterization and performance estimation; (5)CMOS circuit and logic design; (6)structured design and testing; (7)symbolic layout systems; (8)CMOS subsystem design; and (9)system case studies. Each of the first eight chapters includes a section of student exercises. Overall, the textbook is clearly written and comprehensive. It will especially appeal to the silicon chauvinist. One must look elsewhere for gallium arsenide technology, so useful for flux hardening. There is precious little on the crucial area of system timing problems (e.g., synchronization failures due to metastable operation), for systems of ultra-high-speed and concurrency. Much experimental work has been done on the defining parameters for metastable operation with nMOS technology. Many systems limitations can be found here, if only the experimenter does not reject too much, too soon, or discriminates too severely. Finally, as we push toward quantum-theoretical limits, circuit switching techniques will be replaced with field switching techniques. The book is highly recommended for students and professionals in computer engineering who are interested in the capabilities and limitations of chip-based CMOS super systems.

Access critical reviews of Computing literature here

Become a reviewer for Computing Reviews.

Please enable JavaScript to view thecomments powered by Disqus.

Recommendations