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Calculating worst-case gate delays due to dominant capacitance coupling

Authors:

Florentin Dartu,

Lawrence T. PileggiAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 46 - 51

https://doi.org/10.1145/266021.266033

Published: 13 June 1997 Publication History

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Abstract

In this paper we develop a gate level model that allows us to determinethe best and worst case delay when there is dominant interconnectcoupling. Assuming that the gate input windows oftransition are known, the model can predict the worst and bestcase noise, as well as the worst and best case impact on delay. Thisis done in terms of a Ceff based gate model under general RCinterconnect loading conditions.

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Cited By

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Guo LXU WWang H(2023)Exploiting signal skew to reduce delay uncertainty for chiplet interconnectsIEICE Electronics Express10.1587/elex.20.2023018820:13(20230188-20230188)Online publication date: 10-Jul-2023
https://doi.org/10.1587/elex.20.20230188
Sayil SSayil S(2022)Single Event Soft ErrorsNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_6(81-111)Online publication date: 1-Sep-2022
https://doi.org/10.1007/978-3-031-12751-9_6
Sayil SSayil S(2016)Modeling of Single Event Coupling Delay and Speedup EffectsSoft Error Mechanisms, Modeling and Mitigation10.1007/978-3-319-30607-0_6(63-74)Online publication date: 26-Feb-2016
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Calculating worst-case gate delays due to dominant capacitance coupling

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Information & Contributors

Information

Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

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DAC97

Sponsor:

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IEEE-CAS

DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

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https://doi.org/10.1587/elex.20.20230188
Sayil SSayil S(2022)Single Event Soft ErrorsNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_6(81-111)Online publication date: 1-Sep-2022
https://doi.org/10.1007/978-3-031-12751-9_6
Sayil SSayil S(2016)Modeling of Single Event Coupling Delay and Speedup EffectsSoft Error Mechanisms, Modeling and Mitigation10.1007/978-3-319-30607-0_6(63-74)Online publication date: 26-Feb-2016
https://doi.org/10.1007/978-3-319-30607-0_6
Sayil SYuan L(2015)Modeling single event crosstalk speedup in nanometer technologiesMicroelectronics Journal10.1016/j.mejo.2015.02.00246:5(343-350)Online publication date: May-2015
https://doi.org/10.1016/j.mejo.2015.02.002
FIGUEIREDO MAGUIAR R(2012)A Jitter Insertion and Accumulation Model for Clock RepeatersIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.2430E95.A:12(2430-2442)Online publication date: 2012
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Harizi HHäußler ROlbrich MBarke ELevitan S(2007)Efficient modeling techniques for dynamic voltage drop analysisProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278657(706-711)Online publication date: 4-Jun-2007
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