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Hardware support for accurate per-task energy metering in multicore systems

Published: 01 December 2013 Publication History

Abstract

Accurately determining the energy consumed by each task in a system will become of prominent importance in future multicore-based systems because it offers several benefits, including (i) better application energy/performance optimizations, (ii) improved energy-aware task scheduling, and (iii) energy-aware billing in data centers. Unfortunately, existing methods for energy metering in multicores fail to provide accurate energy estimates for each task when several tasks run simultaneously.
This article makes a case for accurate Per-Task Energy Metering (PTEM) based on tracking the resource utilization and occupancy of each task. Different hardware implementations with different trade-offs between energy prediction accuracy and hardware-implementation complexity are proposed. Our evaluation shows that the energy consumed in a multicore by each task can be accurately measured. For a 32-core, 2-way, simultaneous multithreaded core setup, PTEM reduces the average accuracy error from more than 12% when our hardware support is not used to less than 4% when it is used. The maximum observed error for any task in the workload we used reduces from 58% down to 9% when our hardware support is used.

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Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 10, Issue 4
December 2013
1046 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/2541228
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 December 2013
Accepted: 01 October 2013
Revised: 01 September 2013
Received: 01 June 2013
Published in TACO Volume 10, Issue 4

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Author Tags

  1. Power modeling
  2. chip multiprocessors
  3. hardware counters
  4. modeling and estimation
  5. per-task energy attribution
  6. simultaneous multithreaded

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  • (2017)Time and energy modeling of a high-performance multi-threaded Cholesky factorizationThe Journal of Supercomputing10.1007/s11227-016-1654-673:1(139-151)Online publication date: 1-Jan-2017
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  • (2016)Data Center Energy Consumption Modeling: A SurveyIEEE Communications Surveys & Tutorials10.1109/COMST.2015.248118318:1(732-794)Online publication date: Sep-2017
  • (2016)Low-Cost Hardware Infrastructure for Runtime Thread Level Energy AccountingProceedings of the 29th International Conference on Architecture of Computing Systems -- ARCS 2016 - Volume 963710.1007/978-3-319-30695-7_21(277-289)Online publication date: 4-Apr-2016
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  • (2015)Time and energy modeling of high–performance Level-3 BLAS on x86 architecturesSimulation Modelling Practice and Theory10.1016/j.simpat.2015.04.00355(77-94)Online publication date: Jun-2015
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