A Low-Power Block-Matching Cell for Video Compression

1. LeGall, D., “MPEG: A video compression standard for multimedia applications.” Communications of ACM, pp. 47-58, April 1991.

2. “Video codec for audiovisual services at p*64 kb/s,” August 1990. CCITT Recommendation H.261, CDM XV-R 37-E, International Telegraph and Telephone Consultative Committee (CCITT).

3. Chen, T.-H., “A cost-effective three-step hierarchical search block-matching chip for motion estimation.” IEEE Journal of Solid State Circuits 33(8), pp. 1253-1258, 1998.

   Article  Google Scholar 

4. Mizuno, M., Ooi, Y., Hayashi, N., Goto, J., Hozumi, M., Furuta, K., Shibayama, A., Nakazawa, Y., Ohnishi, O., Zhu, S., Yokoyama, Y., Katayama, Y., Takano, H., Miki, N., Senda, Y., Tamitani, I., and Yamashina, M., “A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation.” IEEE Journal of Solid State Circuits 32(11), pp. 1807-1815, 1997.

   Article  Google Scholar 

5. Liou, M., “Overview of the p*64 kbits/s video coding standard.” Communications of ACM, pp. 60-63, April 1991.

6. “Line transmission of non-telephone signals video coding for low bitrate communication,” July 1995. ITU-T DRAFT H.263.

7. Yang, K.-M., Sun, M.-T., and Wu, L., “A family of VLSI designs for the motion compensation block-matching algorithm.” IEEE Transactions on Circuits and Systems 36, pp. 1317-1325, October 1989.

   Article  Google Scholar 

8. Vos, L. D. and Stegherr, M., “Parametrizable VLSI architectures for the full-search block-matching algorithm.” IEEE Transactions on Circuits and Systems 36, pp. 1309-1316, October 1989.

   Article  Google Scholar 

9. Suguri, K., Minani, T., Matsuda, H., Kusaba, R., Kondo, T., Kasai, R., Watanabe, T., Sato, H., Shibata, N., Tashiro, Y., Izuoka, T., Shimizu, A., and Kotera, H., “A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding.” IEEE Journal of Solid State Circuits 31(11), pp. 1733-1741, 1996.

   Article  Google Scholar 

10. Chandrakasan, A. P., Burstein, A., and Brodersen, R. W., “A low power chipset for a portable multimedia I/O terminal.” IEEE Journal of Solid State Circuits 29, pp. 1415-1428, December 1994.

    Article  Google Scholar 

11. Cauwenberghs, G. and Pedroni,V., “A low-power CMOS analog vector quantizer.” IEEE Journal of Solid State Circuits 32(8), pp. 1278-1283, 1997.

    Article  Google Scholar 

12. Gregorian, R. and Temes, G., Analog MOS Integrated Circuits for Signal Processing. Wiley, New York, 1986.

    Google Scholar 

13. Ozdemir, H., Kepkep, A., Pamir, B., Leblebici, Y., and Cilingiroglu, U., “A capacitive threshold-logic gate.” IEEE Journal of Solid State Circuits 31(8), pp. 1141-1150, 1996.

    Article  Google Scholar 

14. Weste, N. and Eshraghian, K., Principles of CMOSVLSI Design: A Systems Perspective. Addison-Wesley, Reading, MA, 1994.

    Google Scholar 

15. Sheu, B. and Hu, C., “Switch-induced error voltage on a switched capacitor.” IEEE Journal of Solid State Circuits 19, pp. 519-525, August 1984.

    Article  Google Scholar 

16. Pergrom, M., Duinmaijer, A. C. J., and Welbers, A. P., “Matching properties of MOS transistors.” IEEE Journal of Solid State Circuits 24, pp. 1433-1440, October 1989.

    Article  Google Scholar 

17. Bastos, J., Stayaert, M., Pergoot, A., and Sansen,W., “Mismatch characterization of submicron MOS transistors.” Analog Integrated Circuits and Signal Processing 12, pp. 95-106, 1997.

    Article  Google Scholar 

18. AVANT, Star-Hspice data-sheet. http://www.avanticorp.com, 1999.

19. Velghe, R., Klaassen, D., and Klaassen, F., “Compact MOS modeling for analog circuit simulation.” in IEDM Tech. Dig., pp. 485-488, 1993.

20. Wong, H., Frank, D., Solomon, P., Wann, C., and Welser, J., “Nanoscale CMOS,” in Proceedings of IEEE 87(4), pp. 537-570, 1999.

    Article  Google Scholar 

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