article

Energy-effective issue logic

Authors:

Daniele Folegnani,

Antonio GonzálezAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 29, Issue 2

Pages 230 - 239

https://doi.org/10.1145/384285.379266

Published: 01 May 2001 Publication History

Abstract

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the issue logic depends on several architectural parameters, the instruction issue queue size being one of the most important. In this paper we present a technique to reduce the energy consumption of the issue logic of a high-performance superscalar processor. The proposed technique is based on the observation that the conventional issue logic wastes a significant amount of energy for useless activity. In particular, the wake-up of empty entries and operands that are ready represents an important source of energy waste. Besides, we propose a mechanism to dynamically reduce the effective size of the instruction queue. We show that on average the effective instruction queue size can be reduced by a factor of 26% with minimal impact on performance. This reduction together with the energy saved for empty and ready entries result in about 90.7% reduction in the energy consumed by the wake-up logic, which represents 14.9% of the total energy of the assumed processor.

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Energy-effective issue logic

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by ...

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 29, Issue 2

Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)

May 2001

262 pages

ISSN:0163-5964

DOI:10.1145/384285

Editor:
Per Stenström
Chalmers Univ. of Technology

Issue’s Table of Contents

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
June 2001
289 pages
ISBN:0769511627
DOI:10.1145/379240
Chairman:
Per Stenström
Chalmers Univ. of Technology

Copyright © 2001 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2001

Published in SIGARCH Volume 29, Issue 2

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MATSUDA YSHIOYA RANDO H(2022)Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag ComparisonIEICE Transactions on Information and Systems10.1587/transinf.2021EDP7174E105.D:2(320-332)Online publication date: 1-Feb-2022
https://doi.org/10.1587/transinf.2021EDP7174
Soliman WPriya BReddy DAnusha PReddy D(2021)Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing UtilizationIEEE Sensors Journal10.1109/JSEN.2020.302036221:2(2334-2345)Online publication date: 15-Jan-2021
https://doi.org/10.1109/JSEN.2020.3020362
Criswell KAdegbija T(2019)A Survey of Phase Classification Techniques for Characterizing Variable Application BehaviorIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2019.292978131:1(224-236)Online publication date: 17-Dec-2019
https://dl.acm.org/doi/10.1109/TPDS.2019.2929781
Adegbija TRogacs APatel CGordon-Ross A(2018)Microprocessor Optimizations for the Internet of Things: A SurveyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271778237:1(7-20)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2717782
Jha SHeirman WFalcón ATubella JGonzález AEeckhout L(2017)Shared resource aware scheduling on power-constrained tiled many-core processorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.10.001100:C(30-41)Online publication date: 1-Feb-2017
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Adegbija TGordon-Ross A(2016)Phase-Based Dynamic Instruction Window Optimization for Embedded Systems2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.96(397-402)Online publication date: Jul-2016
https://doi.org/10.1109/ISVLSI.2016.96
Guney IYildiz ABayindir ISerdaroglu KBayik UKucuk G(2015)A Machine Learning Approach for a Scalable, Energy-Efficient Utility-Based Cache PartitioningHigh Performance Computing10.1007/978-3-319-20119-1_29(409-421)Online publication date: 20-Jun-2015
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KORA YYAMAGUCHI KANDO H(2014)MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available ParallelismIEICE Transactions on Information and Systems10.1587/transinf.2014EDP7177E97.D:12(3110-3123)Online publication date: 2014
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Wu YChen YChen TGuo QZhang L(2014)An Elastic Architecture Adaptable to Various Application ScenariosJournal of Computer Science and Technology10.1007/s11390-014-1425-x29:2(227-238)Online publication date: 23-Mar-2014
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