Article

Energy-effective issue logic

Authors:

Daniele Folegnani,

Antonio GonzálezAuthors Info & Claims

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture

Pages 230 - 239

https://doi.org/10.1145/379240.379266

Published: 01 May 2001 Publication History

Abstract

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the issue logic depends on several architectural parameters, the instruction issue queue size being one of the most important. In this paper we present a technique to reduce the energy consumption of the issue logic of a high-performance superscalar processor. The proposed technique is based on the observation that the conventional issue logic wastes a significant amount of energy for useless activity. In particular, the wake-up of empty entries and operands that are ready represents an important source of energy waste. Besides, we propose a mechanism to dynamically reduce the effective size of the instruction queue. We show that on average the effective instruction queue size can be reduced by a factor of 26% with minimal impact on performance. This reduction together with the energy saved for empty and ready entries result in about 90.7% reduction in the energy consumed by the wake-up logic, which represents 14.9% of the total energy of the assumed processor.

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Published In

cover image ACM Conferences

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture

June 2001

289 pages

ISBN:0769511627

DOI:10.1145/379240

Chairman:
Per Stenström
Chalmers Univ. of Technology

ACM SIGARCH Computer Architecture News Volume 29, Issue 2
Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)
May 2001
262 pages
ISSN:0163-5964
DOI:10.1145/384285
Editor:
Per Stenström
Chalmers Univ. of Technology
Issue’s Table of Contents

Copyright © 2001 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\TCCA: TC on Computer Arhitecture

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Association for Computing Machinery

New York, NY, United States

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Published: 01 May 2001

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ISCA01: 28th International Symposium on Computer Architecture

June 30 - July 4, 2001

Göteborg, Sweden

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ISCA '01 Paper Acceptance Rate 24 of 163 submissions, 15%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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https://dl.acm.org/doi/10.1145/3391443
Natarajan ARamachandran AMittal N(2020)FEASTACM Transactions on Parallel Computing10.1145/33914387:2(1-64)Online publication date: 18-May-2020
https://dl.acm.org/doi/10.1145/3391438
Ferles KVan Geffen JDillig ISmaragdakis Y(2018)Symbolic reasoning for automatic signal placementACM SIGPLAN Notices10.1145/3296979.319239553:4(120-134)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192395
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Nodehi Sabet AQiu JZhao Z(2018)TigrACM SIGPLAN Notices10.1145/3296957.317318053:2(622-636)Online publication date: 19-Mar-2018
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Tran KJimborean ACarlson TKoukos KSjälander MKaxiras SFoster JGrossman D(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192393(328-343)Online publication date: 11-Jun-2018
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Brandalero MBeck A(2017)A mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streamsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130724(1472-1477)Online publication date: 27-Mar-2017
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