research-article

Design of 9-transistor single bit full adder

Author:

Manoj KumarAuthors Info & Claims

CCSEIT '12: Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology

Pages 337 - 340

https://doi.org/10.1145/2393216.2393273

Published: 26 October 2012 Publication History

Abstract

Here, new low power single bit full adder using 9 transistors has been presented. The proposed adder has the advantage of low power consumption with less area requirements due fewer numbers of transistors. Low power goal has been achieved at circuit level by designing the adder with optimized XNOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in the design. The circuits have been simulated in 0.18μm CMOS technology with SPICE. The adder shows power dissipation of 2.0773mW with maximum output delay of 1.86ps at supply voltage of 3.3V. Simulations have been carried out with varying supply voltage 3.3V to 2.7V. Power consumption of proposed full adder has been compared with earlier reported circuits and proposed circuit shows better results.

References

[1]

Ekekwe, N. and. Etienne-cummings, R. 2006. Power dissipation sources and possible control techniques in deep ultra submicron CMOS technologies. Microelectronics Journals, 37 (May 2006), 851--860.

[2]

Leblebici, Y. and. Kang, S. M. 1999. CMOS Digital Integrated Circuits, Singapore: Mc Graw Hill, 2nd edition.

[3]

Weste, N. and Eshraghian, K. 1993. Principles of CMOS VLSI Design, A System Perspective. Addison-Wesley.

Digital Library

[4]

Zimmermann, R. and Fichtner, W. 1997. Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid State Circuits, 32, 7(Jul. 1997), 1079--1090.

[5]

Shams, Ahmed M., Darwish, T. K., and Bayoumi, M. A. 2002. Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Transactions on Very Large Scale Integrations (VLSI) Systems, 10, 1(Feb.2002), 20--29.

Digital Library

[6]

Adu-Shama, E. and Bayoumi, M. 1996. A new cell for low power adders IEEE International Symposium on Circuits and systems, 1996, 1014--1017.

[7]

Zhuang N. and Wu, H. 1992. A new design of the CMOS full adder. IEEE J. Solid-State Circuits, 27, 5(May 1992), 840--844.

[8]

Al-Sheraidah, Y. J., Wang Sha, A. Y., and Jin-Gyun Chung, E. 2004. A novel multiplexer-based low-power full adder. IEEE Transactions on Circuits and Systems: Express Briefs, 51, 7(Jul. 2004).

[9]

Shalem, R., John, E., and John, L. K. 1999. A novel low-power energy recovery full adder cell. In Proc. Great Lakes Symp. VLSI, Feb. 1999, 380--383.

Digital Library

[10]

Chang, C. H,. Gu, J., and Zhang, M. 2005. A review of 0.18μm full adder performances for tree structured arithmetic circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 6(Jun.2005), 686--695.

Digital Library

[11]

Bui, H. T., Wang, Y., and Jiang, Y. 2002. Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates. IEEE Trans. Circuits Syst. II, Analog Digital Signal Process, 49, 1(Jan. 2002), 25--30.

[12]

Zhang, M., Gu J., and Chang, C. H.2003. A novel hybrid pass logic with static CMOS output drive full-adder cell. In proc. IEEE Int. Symp. Circuits Systems, May 2003, 317--320.

[13]

Goel, S., Kumar, A., and Bayoumi, M. A. 2006. Design of robust, energy efficient full adders for deep sub micrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14, 12(Dec. 2006), 1309--1321.

Digital Library

[14]

Shams, A. M. and Bayoumi, M. 2000. A novel high-performance CMOS1-bit full adder cell. IEEE Trans. Circuits Syst. II, Analog Digital Signal Process, 47, 5(May 2000), 478--481.

[15]

Shams, A. M. and Magdy A, 1997. A structured approach for designing low power adders. Conference Record of the Thirty-First Asilomar Conference on Signals, Systems & Computers, Nov. 1997, 757--761.

Cited By

Ganesh GRaavi M(2021)Implementation and comparison of Boolean logic for different Nano Scaling technologies2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)10.1109/ICEECCOT52851.2021.9707983(312-317)Online publication date: 10-Dec-2021
https://doi.org/10.1109/ICEECCOT52851.2021.9707983
Bhardwaj AChauhan VKumar M(2019)Design of CMOS Based D Flip-Flop with Different Low Power Techniques2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)10.1109/SPIN.2019.8711610(834-839)Online publication date: Mar-2019
https://doi.org/10.1109/SPIN.2019.8711610
Arun Kumar M(2014)Design of low power split path Data Driven Dynamic ripple carry adders2014 International Conference on Computing for Sustainable Global Development (INDIACom)10.1109/IndiaCom.2014.6828008(37-41)Online publication date: Mar-2014
https://doi.org/10.1109/IndiaCom.2014.6828008

Design of 9-transistor single bit full adder
1. Hardware
2. Networks
  1. Network types
    1. Ad hoc networks

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CCSEIT '12: Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology

October 2012

800 pages

ISBN:9781450313100

DOI:10.1145/2393216

General Chairs:
Natarajan Meghanathan
Jackson State University
,
Michal Wozniak
Wroclaw University of Technology, Poland

Copyright © 2012 ACM.

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Avinashilingam University: Avinashilingam University

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New York, NY, United States

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Published: 26 October 2012

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Avinashilingam University

CCSEIT '12: The Second International Conference on Computational Science, Engineering

October 26 - 28, 2012

Coimbatore UNK, India

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Cited By

Ganesh GRaavi M(2021)Implementation and comparison of Boolean logic for different Nano Scaling technologies2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT)10.1109/ICEECCOT52851.2021.9707983(312-317)Online publication date: 10-Dec-2021
https://doi.org/10.1109/ICEECCOT52851.2021.9707983
Bhardwaj AChauhan VKumar M(2019)Design of CMOS Based D Flip-Flop with Different Low Power Techniques2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)10.1109/SPIN.2019.8711610(834-839)Online publication date: Mar-2019
https://doi.org/10.1109/SPIN.2019.8711610
Arun Kumar M(2014)Design of low power split path Data Driven Dynamic ripple carry adders2014 International Conference on Computing for Sustainable Global Development (INDIACom)10.1109/IndiaCom.2014.6828008(37-41)Online publication date: Mar-2014
https://doi.org/10.1109/IndiaCom.2014.6828008

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