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Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

Authors:

Massoud Pedram,

Xunwei WuAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 339 - 344

https://doi.org/10.1145/368434.368670

Published: 28 January 2000 Publication History

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Cited By

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Sana PSatyam M(2011)A low power secure logic style to counteract differential power analysis attacksProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783557(1-4)Online publication date: Apr-2011
https://doi.org/10.1109/VDAT.2011.5783557
Esmaeili SAl-Khalili ACowan G(2009)A study on the effects of temperature and loading on the power consumption in energy recovery resonant clockingProceedings of the 2009 conference on Information Science, Technology and Applications10.1145/1551950.1551978(91-95)Online publication date: 20-Mar-2009
https://dl.acm.org/doi/10.1145/1551950.1551978
Hang GTang T(2005)Adiabatic CMOS gate and adiabatic circuit design for low-power applicationsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121022(803-808)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121022
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Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
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ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2000

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Cited By

View all

Sana PSatyam M(2011)A low power secure logic style to counteract differential power analysis attacksProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783557(1-4)Online publication date: Apr-2011
https://doi.org/10.1109/VDAT.2011.5783557
Esmaeili SAl-Khalili ACowan G(2009)A study on the effects of temperature and loading on the power consumption in energy recovery resonant clockingProceedings of the 2009 conference on Information Science, Technology and Applications10.1145/1551950.1551978(91-95)Online publication date: 20-Mar-2009
https://dl.acm.org/doi/10.1145/1551950.1551978
Hang GTang T(2005)Adiabatic CMOS gate and adiabatic circuit design for low-power applicationsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121022(803-808)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121022
Guoqiang Hang (2005)Adiabatic CMOS gate and adiabatic circuit design for low-power applicationsProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466466(803-808)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466466
Wu XHang GMassoud P(2002)Low power DCVSL circuits employing AC power supplyScience in China Series F Information Sciences10.1360/02yf902145:3(232-240)Online publication date: Jun-2002
https://doi.org/10.1360/02yf9021
Hang GWu X(2002)Improved structure for adiabatic CMOS circuits designMicroelectronics Journal10.1016/S0026-2692(02)00011-333:5-6(403-407)Online publication date: May-2002
https://doi.org/10.1016/S0026-2692(02)00011-3

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