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Minimization of chip size and power consumption of high-speed VLSI buffers

Authors:

D. Zhou,

X. Y. LiuAuthors Info & Claims

ISPD '97: Proceedings of the 1997 international symposium on Physical design

Pages 186 - 191

https://doi.org/10.1145/267665.267711

Published: 01 April 1997 Publication History

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https://doi.org/10.1007/s42452-024-05979-y
Amelifard BFallah FPedram M(2019)Low-power fanout optimization using multi threshold voltages and multi channel lengthsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201399228:4(478-489)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2009.2013992
Zhou DLi R(2018)Design and verification of high-speed VLSI physical designJournal of Computer Science and Technology10.1007/s11390-005-0147-520:2(147-165)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s11390-005-0147-5
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Index Terms

Minimization of chip size and power consumption of high-speed VLSI buffers
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design

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Published In

ISPD '97: Proceedings of the 1997 international symposium on Physical design

April 1997

230 pages

ISBN:0897919270

DOI:10.1145/267665

Chairmen:
Andrew B. Kahng
Univ. of California, Los Angeles, and Cadence Design Systems, San Jose, CA
,
Majid Sarrafzadeh
Northwestern Univ., Evanston, IL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1997

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Sponsor:

SIGDA

ISPD97: 1997 International Symposium on Physical Design

April 14 - 16, 1997

California, Napa Valley, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

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March 16 - 19, 2025

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Cited By

View all

Wang SWang ZWang XXia HWang QDuan PLeng FTian JHuang HIp WYung K(2024)Influence of N2 plasma treatment on properties of black phosphorus devices in space electronic systemsDiscover Applied Sciences10.1007/s42452-024-05979-y6:6Online publication date: 30-May-2024
https://doi.org/10.1007/s42452-024-05979-y
Amelifard BFallah FPedram M(2019)Low-power fanout optimization using multi threshold voltages and multi channel lengthsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201399228:4(478-489)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2009.2013992
Zhou DLi R(2018)Design and verification of high-speed VLSI physical designJournal of Computer Science and Technology10.1007/s11390-005-0147-520:2(147-165)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s11390-005-0147-5
Maalej ABen-Romdhane MRebai CGhazel A(2009)Pseudo-random oscillator design for multistandard RF Non Uniformly Sampling receiver2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era10.1109/DTIS.2009.4938022(47-51)Online publication date: Apr-2009
https://doi.org/10.1109/DTIS.2009.4938022
Amelifard BFallah FPedarm MNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Low-power fanout optimization using MTCMOS and multi-Vt techniquesProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165652(334-337)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165652
Li RZhou DLiu JZeng X(2006)Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin netsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85267224:12(1915-1924)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.852672
Ruiming Li Dian Zhou Jin Liu Xuan Zeng (2005)Power-Optimal Simultaneous Buffer Insertion/Sizing and Uniform Wire Sizing for Single Long Wires2005 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2005.1464537(113-116)Online publication date: 2005
https://doi.org/10.1109/ISCAS.2005.1464537
Li RZhou DLiu JZeng X(2003)Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire SizingProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009948Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009948
Ruiming Li Dian Zhou Jin Liu Xuan Zeng (2003)Power-optimal simultaneous buffer insertion/sizing and wire sizingICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159741(581-586)Online publication date: 2003
https://doi.org/10.1109/ICCAD.2003.159741

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High-speed VLSI arithmetic processor architectures using hybrid number representation

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