Article

Free access

Low power logic synthesis under a general delay model

Authors:

Unni Narayanan,

C. L. LiuAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 209 - 214

https://doi.org/10.1145/280756.280900

Published: 10 August 1998 Publication History

Abstract

Till now most efforts in low power lo gic synthesis have oncentr ated on minimizing the total switching activity of a circuit under a zero delay model. This simplification ignor es the effe cts of glitch tr ansitions which may contribute as much as 30% of the total power c onsumption of a circuit. Hence, low power logic synthesis techniques which optimize power under a zer o delay model ar e often not successful in attaining “r eal” p ower savings as measured under a more accurate gener al delay model. In pr actice, to ac curately estimate the switching activity in a circuit under a gener al delay model can be computationally expensive. Hence, to repeatedly call accurate but slow power estimation tools to dir ect the synthesis flow is not a viable approach in the design of low power synthesis tools. In this pap er we take advantage of a fast method for estimating the total switching activity in a circuit under a general delay model to synthesize low power circuits. Sp ecific ally,we use the appr oximation as a basis for algorithms that solve two problems: (1) low power te chnolo gy decomposition of gates under a gener al delay model (2) low power r etiming of sequential cir cuits under a general delay model.

References

[1]

Daniel Brand and Chandu Visweswariah. Inaccuracies in power estimation during logic synthesis. In International Conference on Computer-Aided Design, pages 388-384, 1996.

Digital Library

[2]

Anantha P. Chandrakasan and Robert W. Broderson. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995.

Digital Library

[3]

Jose C. Costa, Jose C. Monteiro, and Srinivas Devadas. Switching activity estimation using limited depth reconvergent path analysis, in International Symposium on low power electronics and design, pages 184-189, 1997.

Digital Library

[4]

Eric Lehman, Yosinori Watanabe, Joel Grodstein, and Heather Harkness. Logic decomposition during technology mapping. In International Conference on Compuer-Aided Design, pages 264-271, 1995.

Digital Library

[5]

Charles E. Leiserson and James B. Saxe. Retiming synchronous circuitry. Algorithmica, 6:5-35, 1991.

Digital Library

[6]

Jeroen Leitjen, Jef van Meerbergen, and Jochen Jess. Analysis and reduction of glitches in synchronous network. Received: 1996.

[7]

Jose Monteiro and Srinivas Devadas. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Kluwer Academic Publishers, 1997.

Digital Library

[8]

F. Najm. Transition density, a stochastic measure of activity in digital circuits, in International Conference on Compuer-Aided Design, pages 644-649, June 1991.

Digital Library

[9]

U. Narayanan, Hon Wai Leong, Ki-Seok Chung, and C. L. Liu. Low power multiplexer decomposition. In International Symposium on low power electronics and design, pages 269-274, 1997.

Digital Library

[10]

U. Narayanan and C. L. Liu. Low power logic synthesis for xor based circuits. In International Conference on Computer-Aided Design, 1997.

Digital Library

[11]

K. Parker and E. McCluskey. Probabilistic treatment of general combinational networks. IEEE Transactions on Electronic Computers, C-24(6):668-670, 1975.

Digital Library

[12]

G. I. Stamoulis. A monte-carlo approach for the accurate and efficient estimation of average transition probabilities in sequential logic circuits. In IEEE Custom Integrated Circuits Conference, pages 221-224, 1996.

[13]

Sarma B. K. Vrudhula and Hong-Yu Xie. Techniques for cmos power estimation and logic synthesis for low power. In International Workshop on Low Power Design, pages 21-26, 1994.

[14]

Nell H. E. Weste and Kamran Eshraghian. Principles of CMOS VLSI Design: A Systems Perspective. Addison-Wesley, 1993.

Digital Library

[15]

Hai Zhou and D. F. Wong. An exact gate decomposition algorithm for low-power technology mapping. In International Conference on Computer-Aided Design, 1997.

Digital Library

Cited By

Dinh QChen DWong M(2010)BDD-based circuit restructuring for reducing dynamic power2010 IEEE International Conference on Computer Design10.1109/ICCD.2010.5647524(548-554)Online publication date: Oct-2010
https://doi.org/10.1109/ICCD.2010.5647524
Liu JLi WZhang L(2010)Two Coding UARTs Low-Power Simulation Analysis Based on Gate Switching Activity Rate2010 International Conference on Biomedical Engineering and Computer Science10.1109/ICBECS.2010.5462423(1-3)Online publication date: Apr-2010
https://doi.org/10.1109/ICBECS.2010.5462423
Zhang WWilliamson JShang L(2010)Power DissipationLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_2(41-80)Online publication date: 25-Oct-2010
https://doi.org/10.1007/978-1-4419-7418-1_2
Show More Cited By

Index Terms

Low power logic synthesis under a general delay model

Recommendations

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
VLSID '97: Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

With the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end we introduce algebraic procedures for node extraction ...
Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits
Algorithmic techniques for logic synthesis of low power vlsi circuits

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Copyright © 1998 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEEE-EDS: Electronic Devices Society
SIGDA: ACM Special Interest Group on Design Automation
IEEE-SSCS: Solid Stat Circuits Council
IEEE-CAS: Circuits & Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISLPED98

Sponsor:

IEEE-EDS
SIGDA
IEEE-SSCS
IEEE-CAS

ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
375
Total Downloads

Downloads (Last 12 months)20
Downloads (Last 6 weeks)1

Reflects downloads up to 17 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Dinh QChen DWong M(2010)BDD-based circuit restructuring for reducing dynamic power2010 IEEE International Conference on Computer Design10.1109/ICCD.2010.5647524(548-554)Online publication date: Oct-2010
https://doi.org/10.1109/ICCD.2010.5647524
Liu JLi WZhang L(2010)Two Coding UARTs Low-Power Simulation Analysis Based on Gate Switching Activity Rate2010 International Conference on Biomedical Engineering and Computer Science10.1109/ICBECS.2010.5462423(1-3)Online publication date: Apr-2010
https://doi.org/10.1109/ICBECS.2010.5462423
Zhang WWilliamson JShang L(2010)Power DissipationLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_2(41-80)Online publication date: 25-Oct-2010
https://doi.org/10.1007/978-1-4419-7418-1_2
Hu YLin YHe LTuan T(2008)Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retimingACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1344418.134442613:2(1-29)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344426
Chang HHuang JChen C(2007)Input Selection Encoding for Low Power Multiplexer Tree2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VDAT.2007.373253(1-4)Online publication date: Apr-2007
https://doi.org/10.1109/VDAT.2007.373253
Patra PNarayanan UKim T(2001)Phase assignment for synthesis of low-power domino circuitsElectronics Letters10.1049/el:2001055737:13(814)Online publication date: 2001
https://doi.org/10.1049/el:20010557
Patra PNarayanan U(1999)Automated phase assignment for the synthesis of low power domino circuitsProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309964(379-384)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309964
Narayanan UStamoulis GRoy R(1999)Characterizing individual gate power sensitivity in low power designProceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)10.1109/ICVD.1999.745275(625-628)Online publication date: 1999
https://doi.org/10.1109/ICVD.1999.745275
Patra PNarayanan U(1999)Automated phase assignment for the synthesis of low power domino circuitsProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781345(379-384)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781345

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents