Article

Free access

Parallel algorithms for power estimation

Authors:

Victor Kim,

Prithviraj BanerjeeAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 672 - 677

https://doi.org/10.1145/277044.277215

Published: 01 May 1998 Publication History

PDF eReader

Abstract

Sev eral tec hniques currently exist for estimating the pow er dissipation of combinational and sequen tialcircuits using exhaustive sim ulation,Monte Carlo sampling, and probabilistic estimation. Exhaustive sim ulation and Monte Carlo sampling techniques can be highly reliable but often require long runtimes. This paper presents a comprehensive study of pattern-p artitioning and circuit-p artitioning parallelization schemes for those tw o methodologies in the con text of distributed-memory multiprocessing systems. Issues in pip eline dev ent-driv en simulation and dynamic load balancing are addressed. Experimental results are presented for an IBM SP-2 system and a netw ork of HP-9000 workstations. F or instance, runtimes have been reduced from over 3 hours to under 20 minutes in one case.

References

[1]

P. Banerjee, )Parallel Algorithms for VLSI Computer Aided Design, Englewood Cliffs, NJ: PTR Prentice Hall, 1994.

Digital Library

Google Scholar

[2]

W. Groppe,E.Lusk,and A.Skjellum, Using MPI: Portable Parallel Prognnnming with the Message Passing Interface MIT Press, 1994.

Digital Library

Google Scholar

[3]

C.X.Huang,B.Zhang An-Chang Deng and B. Swiraki "The design and implementation of power Mill,ACM/IEEE International Symposimn on Low Power Design,PP 105-109, 1995.

Digital Library

Google Scholar

[4]

V. Kim, "Parallel Algorithms for CMOS Power Estimation,'' Masters Thesis, Northwestern University, 1997, available at http//www.ece.nwn.edu/cpde/Tech Reports/:

Google Scholar

[5]

D/Krishnaswamy, P. Banerjee, E. Rudnick and J.Patel,Asynchronous parallel algorithms for test set partitioned parallel fault simulation,Proc. Workshop on Pamllel and Distributed Simulation(PADS-97),Jun. 1997.

Digital Library

Google Scholar

[6]

P.Lukuch"Evaluation of three approaches to parallel logic simulation on a distributed memory multiprocessor,* Proc. 26th Annual Simulation Symposium, Arlington,pp.2-11,. 1993.

Google Scholar

[7]

L.W.Nagel,Spice2:. a computer program to simulate semiconductor circuits," Memo,ERL-MS20 . Dept. Electrical Engineering and Computer Science, University of California at Berkeley, May 9, 1975.

Google Scholar

[8]

F.N.Najm "Power estimation techniques for integrated circuits," IEEE,Trans.VLSI,vol.,2 ' no.4,pp.492- 499,Dec 1994.

Digital Library

Google Scholar

[9]

F.Orguner C Aykanat, and 0. Khalid, "Logic fault simulation on a vector hypercube multiprocessor", Pro 3rd Int. Conf. Hypereube Coneulrrent Conq~uters Applications,H:1108-1116,Jan.1988.

Digital Library

Google Scholar

[10]

V.Saxena,"Statistical power estimation for sequential CMOS circuits," Masters Thesis, University of Illinois, 1996.

Google Scholar

[11]

Synopsys Corp.http//www.synopsys.com/producrs/ power/power,html.1997.

Google Scholar

[12]

C.Terman "RSIM: A logic level timing simulator, Proc.Int. Conf.comfuter Design pages. 437-440. Oct. 1983.

Google Scholar

[13]

N.H.E. Weste and K.Eshraghian, Principles of CMOS VLSZ Design: A Systems Perspective, Reading, MA: Addison-Wesley Publishing Company, 1993.

Digital Library

Google Scholar

[14]

M.G. Xakellis and F.N. Najm,"Statistical estimation of the switching activity in digital circuits,"Siet ACM/IEEE Design Automation Conf.,pp728-733 1995.

Digital Library

Google Scholar

Cited By

View all

Chinosi MZafalon RGuardiani C(1999)Parallel mixed-level power simulation based on spatio-temporal circuit partitioningProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309998(562-567)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309998
Chinosi MZafalon RGuardiani C(1999)Parallel mixed-level power simulation based on spatiotemporal circuit partitioningProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781378(562-567)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781378
Chinosi MZafalon RGuardiani C(1999)Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioningProceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)10.1109/CICC.1999.777238(31-34)Online publication date: 1999
https://doi.org/10.1109/CICC.1999.777238

Index Terms

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC98

Sponsor:

EDAC
SIGDA
IEEE-CS

DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
50
Total Downloads

Downloads (Last 12 months)33
Downloads (Last 6 weeks)12

Reflects downloads up to 02 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Chinosi MZafalon RGuardiani C(1999)Parallel mixed-level power simulation based on spatio-temporal circuit partitioningProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309998(562-567)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309998
Chinosi MZafalon RGuardiani C(1999)Parallel mixed-level power simulation based on spatiotemporal circuit partitioningProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781378(562-567)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781378
Chinosi MZafalon RGuardiani C(1999)Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioningProceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)10.1109/CICC.1999.777238(31-34)Online publication date: 1999
https://doi.org/10.1109/CICC.1999.777238

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations