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ASP-DAC 2010: Taipei, Taiwan
- Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010. IEEE 2010, ISBN 978-1-60558-837-7
Embedded systems design techniques
- Jason Helge Anderson:
A PUF design for secure FPGA-based embedded systems. 1-6 - Kai Huang, Luca Santinelli, Jian-Jia Chen
, Lothar Thiele, Giorgio C. Buttazzo:
Adaptive power management for real-time event streams. 7-12 - Bijoy Antony Jose, Sandeep K. Shukla
An alternative polychronous model and synthesis methodology for model-driven embedded software. 13-18 - Shih-Hao Hung
Trace-based performance analysis framework for heterogeneous multicore systems. 19-24
Advanced model order reduction technique
- Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai:
Efficient model reduction of interconnects via double gramians approximation. 25-30 - Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen:
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method. 31-36 - Chi-Un Lei
VISA: versatile impulse structure approximation for time-domain linear macromodeling. 37-42 - Zheng Zhang
An extension of the generalized Hamiltonian method to S-parameter descriptor systems. 43-47
Logic synthesis
- Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang:
Simultaneous slack budgeting and retiming for synchronous circuits optimization. 49-54 - Pongstorn Maidee
A fast SPFD-based rewiring technique. 55-60 - Debasish Das, Jia Wang, Hai Zhou:
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. 61-67
Special session: techniques for efficient energy harvesting and generation for portable and embedded systems
- Naehyuck Chang, Jueun Seo, Donghwa Shin, Younghyun Kim
Room-temperature fuel cells and their integration into portable and embedded systems. 69-74 - Hui Shao, Chi-Ying Tsui
Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design. 75-80 - Clemens Moser, Jian-Jia Chen
Dynamic power management in environmentally powered systems. 81-88 - Chao Lu, Vijay Raghunathan, Kaushik Roy:
Micro-scale energy harvesting: a system design perspective. 89-94
Memory management and compiler techniques
- Yi He, Chun Jason Xue
Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory. 95-100 - Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai:
A new compilation technique for SIMD code generation across basic block boundaries. 101-106 - Wei-Tsun Sun, Zoran Salcic
LibGALS: a library for GALS systems design and modeling. 107-112 - Tiantian Liu, Minming Li
Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. 113-118
Power and signal integrity
- Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin
On-chip power network optimization with decoupling capacitors and controlled-ESRs. 119-124 - Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng:
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. 125-130 - Yongho Lee, Taewhan Kim:
Technique for controlling power-mode transition noise in distributed sleep transistor network. 131-136 - Shuichi Aono, Masaki Unno, Hideki Asai
A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. 137-141
System-level simulation
- Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang (Ric) Huang:
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. 143-148 - Mahesh Nanjundappa, Hiren D. Patel, Bijoy Antony Jose, Sandeep K. Shukla:
SCGPSim: a fast SystemC simulator on GPUs. 149-154 - Hao Shen, Frédéric Pétrot:
A flexible hybrid simulation platform targeting multiple configurable processors SoC. 155-160 - Weiwei Chen, Rainer Dömer
A fast heuristic scheduling algorithm for periodic ConcurrenC models. 161-166
Special session: 3D integration and networks on chips
- Srinivasan Murali, Luca Benini
Design of networks on chips for 3D ICs. 167-168
Emerging memories and 3D ICs
- Paul Falkenstern, Yuan Xie, Yao-Wen Chang
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. 169-174 - Xin Zhao, Sung Kyu Lim
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. 175-180 - Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. 181-186 - Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits. 187-192 - Dimin Niu
Energy and performance driven circuit design for emerging phase-change memory. 193-198
Macromodeling and verification of analog systems
- Saket Gupta, Sachin S. Sapatnekar
Current source modeling in the presence of body bias. 199-204 - Chenjie Gu, Jaijeet S. Roychowdhury:
Manifold construction and parameterization for nonlinear manifold-based model reduction. 205-210 - Hao Yu, Xuexin Liu, Hai Wang, Sheldon X.-D. Tan:
A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel. 211-216 - Kusum Lata
Formal verification of tunnel diode oscillator with temperature variations. 217-222
System-level modelling and analysis
- Jun Zhu, Ingo Sander
Constrained global scheduling of streaming applications on MPSoCs. 223-228 - Jungseob Lee, Shi-Ting Zhou, Nam Sung Kim:
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors. 229-234 - Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay:
Source-level timing annotation for fast and accurate TLM computation model generation. 235-240 - Andrew B. Kahng, Bill Lin, Kambiz Samadi:
Improved on-chip router analytical power and area modeling. 241-246
Special session: recent advancement in post-silicon validation
- Li-C. Wang
Data learning based diagnosis. 247-254 - Valeria Bertacco:
Post-silicon debugging for multi-core designs. 255-258 - Kyungho Kim, Byungtae Kang, Donghyun Kim, Sungchul Lee, Juyong Shin, Hyunchul Shin:
Low-cost design for repair with circuit partitioning. 259-261 - Qiang Xu
On signal tracing in post-silicon validation. 262-267
New techniques for beyond-die routing
- Zigang Xiao, Evangeline F. Y. Young:
CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. 269-274 - Hui Kong, Tan Yan, Martin D. F. Wong
Optimal simultaneous pin assignment and escape routing for dense PCBs. 275-280 - Yukihide Kohira, Atsushi Takahashi
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. 281-286 - Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen:
Obstacle-aware longest path using rectangular pattern detouring in routing grids. 287-292
Analog layout and testing
- Zheng Liu, Lihong Zhang:
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits. 293-298 - Rui He, Lihong Zhang:
Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts. 299-304 - Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki:
Regularity-oriented analog placement with diffusion sharing and well island generation. 305-311 - Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham:
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection. 312-317
New techniques in technology mapping
- Fang-Yu Fan, Hung-Ming Chen, I-Min Liu:
Technology mapping with crosstalk noise avoidance. 319-324 - Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
Fault-tolerant resynthesis with dual-output LUTs. 325-330 - Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang
TRECO: dynamic technology remapping for timing engineering change orders. 331-336 - Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Multi-operand adder synthesis on FPGAs using generalized parallel counters. 337-342
University LSI design contest
- Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa:
Checker-pattern and shared two pixels LOFIC CMOS image sensors. 343-344 - Takahiro Kohara, Woonghee Lee, Koichi Mizobuchi, Shigetoshi Sugawa:
A CMOS image sensor with 2.0-e- random noise and 110-ke- full well capacity using column source follower readout circuits. 345-346 - Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa:
Checkered white-RGB color LOFIC CMOS image sensor. 347-348 - Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda:
A versatile recognition processor for sensor network applications. 349-350 - Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa:
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. 351-352 - Liang-Bi Chen
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development. 353-354 - Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Cascaded time difference amplifier using differential logic delay cell. 355-356 - Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng:
Built-in self at-speed delay binning and calibration mechanism in wireless test platform. 357-358 - Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dynamic voltage domain assignment technique for low power performance manageable cell based design. 359-360 - Hiroshi Fuketa, Masanori Hashimoto
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. 361-362 - Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa:
A 60GHz direct-conversion transmitter in 65nm CMOS technology. 363-364 - Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. 365-366 - Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng:
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. 367-368 - Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. 369-370 - Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Ito:
A WiMAX turbo decoder with tailbiting BIP architecture. 371-372 - Naoto Miyamoto, Tadahiro Ohmi:
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement. 373-374 - Masa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato:
Design and chip implementation of an instruction scheduling free ubiquitous processor. 375-376 - Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano:
MuCCRA-3: a low power dynamically reconfigurable processor array. 377-378 - Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong
Rapid prototyping on a structured ASIC fabric. 379-380 - Jian-Lung Tzeng, Chien-Jen Huang, Yu-Han Yuan, Hsi-Pin Ma:
A high performance low complexity joint transceiver for closed-loop MIMO applications. 381-382
Clock network analysis and optimization
- Zhigang Hao, Guoyong Shi:
A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources. 383-388 - Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen:
Minimizing clock latency range in robust clock tree synthesis. 389-394 - Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. 395-400 - Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy:
Improved clock-gating control scheme for transparent pipeline. 401-406
Test solutions for emerging applications
- Ryuta Nara, Nozomu Togawa
Scan-based attack against elliptic curve cryptosystems. 407-412 - Hideo Fujiwara, Marie Engelene J. Obien
Secure and testable scan design using extended de Bruijn graphs. 413-418 - Janine Chen, Jing Zeng, Li-C. Wang
Correlating system test Fmax with structural test Fmax and process monitoring measurements. 419-424 - Bijan Alizadeh, Masahiro Fujita:
Guided gate-level ATPG for sequential circuits using a high-level test generation approach. 425-430
Power, performance and reliability in SoC design
- Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan:
Optimizing power and performance for reliable on-chip networks. 431-436 - Wei Song
A low latency wormhole router for asynchronous on-chip networks. 437-443 - Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. 444-449 - Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Workload capacity considering NBTI degradation in multi-core systems. 450-455
Designers' forum: State-of-the-art SoCs
- Masanori Kuwahara:
Design and verification methods of Toshiba's wireless LAN baseband SoC. 457-463 - Hiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto, Hideaki Kido, Shoji Muramatsu:
SOC for car navigation system with a 55.3GOPS image recognition engine. 464-465
Advances in modern clock tree routing
- Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
A dual-MST approach for clock network synthesis. 467-473 - Krit Athikulwongse, Xin Zhao, Sung Kyu Lim
Buffered clock tree sizing for skew minimization under power and thermal budgets. 474-479 - Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan:
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. 480-485 - Tak-Yung Kim, Taewhan Kim:
Clock tree embedding for 3D ICs. 486-491
Timing-related testing and diagnosis
- Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng:
Improved weight assignment for logic switching activity during at-speed test pattern generation. 493-498 - Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Graph partition based path selection for testing of small delay defects. 499-504 - Irith Pomeranz, Sudhakar M. Reddy:
Functional and partially-functional skewed-load tests. 505-510 - Ke Peng, Yu Huang, Ruifeng Guo
Emulating and diagnosing IR-drop by using dynamic SDF. 511-516
Application-specific NoC design
- Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
Application-specific 3D Network-on-Chip design using simulated allocation. 517-522 - Wooyoung Jang, David Z. Pan:
A3MAP: architecture-aware analytic mapping for networks-on-chip. 523-528 - Jonas Diemer, Rolf Ernst, Michael Kauschke:
Efficient throughput-guarantees for latency-sensitive networks-on-chip. 529-534 - Bei Yu, Sheqin Dong, Song Chen
Floorplanning and topology generation for application-specific network-on-chip. 535-540
Designers' forum: Is 3D integration an opportunity or just a hype?
- Jin-Fu Li, Cheng-Wen Wu
Is 3D integration an opportunity or just a hype? 541-543 - Kyu-Myung Choi:
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology. 544-545 - Ding-Ming Kwai:
Homogeneous integration for 3D IC with TSV. 546-547
Modern floorplanning and placement techniques
- Qiang Ma, Martin D. F. Wong
Configurable multi-product floorplanning. 549-554 - Jai-Ming Lin, Hsi Hung:
UFO: unified convex optimization algorithms for fixed-outline floorplanning. 555-560 - Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young:
Fixed-outline thermal-aware 3D floorplanning. 561-567 - Yu-Min Lee, Tsung-You Wu, Po-Yi Chiang:
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance. 568-573
Power optimization and estimation in the DSM Era
- Jungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung:
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation. 575-580 - Jun Seomun, Seungwhun Paik, Youngsoo Shin:
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. 581-586 - Quang Dinh, Deming Chen, Martin D. F. Wong
Dynamic power estimation for deep submicron circuits with process variation. 587-592 - Dongkeun Oh
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. 593-599
Design verification and debugging
- Sean Safarpour, Andreas G. Veneris, Farid N. Najm:
Managing verification error traces with bounded model debugging. 601-606 - Po-Hsien Chang, Li-C. Wang
Automatic assertion extraction via sequential data mining of simulation traces. 607-612 - Hu-Hsi Yeh, Chung-Yang Huang:
Automatic constraint generation for guided random simulation. 613-618 - Miroslav N. Velev
A method for debugging of pipelined processors in formal verification by correspondence checking. 619-624
Special session: Dependable silicon design with unreliable components
- James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah
Resilient design in scaled CMOS for energy efficiency. 625 - Siva G. Narendra:
Benefits and barriers for probabilistic design. 626-627 - Lakshmi N. Chakrapani, Krishna V. Palem:
A probabilistic Boolean logic for energy efficient circuit and system design. 628-635
DFM1: Patterning and physical design
- Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan:
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. 637-644 - Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai:
A robust pixel-based RET optimization algorithm independent of initial conditions. 645-650 - Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. 651-656 - Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li:
Dead via minimization by simultaneous routing and redundant via insertion. 657-662
Design and verification for process variation issues
- Xingliang Yuan
Statistical timing verification for transparently latched circuits through structural graph traversal. 663-668 - Jing-Jia Nian, Shihgeng Tsai, Chung-Yang (Ric) Huang:
A unified multi-corner multi-mode static timing analysis engine. 669-674 - Seungwhun Paik, Lee-eun Yu, Youngsoo Shin:
Statistical time borrowing for pulsed-latch circuit designs. 675-680 - Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David T. Blaauw:
Design time body bias selection for parametric yield improvement. 681-688
New advances in high-level synthesis
- Yibo Chen, Yuan Xie, Yu Wang
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment. 689-694 - Taemin Kim, Xun Liu:
A global interconnect reduction technique during high level synthesis. 695-700 - Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama:
Incremental high-level synthesis. 701-706 - Nagaraju Pothineni, Philip Brisk
A high-level synthesis flow for custom instruction set extensions for application-specific processors. 707-712
Special session: ESL: analysis and synthesis of multi-core systems
- Rainer Dömer:
Computer-aided recoding for multi-core systems. 713-716 - Samar Abdi:
TLM automation for multi-core design. 717-724 - Andreas Gerstlauer, Gunar Schirner
Platform modeling for exploration and synthesis. 725-731 - Alan P. Su:
Application of ESL synthesis on GSM edge algorithm for base station. 732-738
DFM2: variation modeling
- Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Analyzing electrical effects of RTA-driven local anneal temperature variation. 739-744 - Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar
Physical design techniques for optimizing RTA-induced variations. 745-750 - Lerong Cheng, Puneet Gupta
On confidence in characterization and application of variation models. 751-756
Power grid analysis
- Baktash Boghrati, Sachin S. Sapatnekar
Incremental solution of power grids using random walks. 757-762 - Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Efficient power grid integrity analysis using on-the-fly error check and reduction. 763-768 - Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. 769-774 - Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
Gate delay estimation in STA under dynamic power supply noise. 775-780
High-level synthesis and optimization for performance and power
- Yibo Chen, Yuan Xie, Yu Wang
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library. 781-786 - Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
Optimizing blocks in an SoC using symbolic code-statement reachability analysis. 787-792 - Jin Cui, Douglas L. Maskell:
High level event driven thermal estimation for thermal aware task allocation and scheduling. 793-798 - Fabrizio Ferrandi
Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs. 799-804
Designers' forum: ESL, the road to glory, or is it not? Real stories about using ESL design methodology in product development
- Koichiro Yamashita:
-Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase. 805-808 - Benjamin Carrión Schäfer
Design of complex image processing systems in ESL. 809-814 - Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang:
PAC duo system power estimation at ESL. 815-820 - W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh:
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. 821-824
DFM3: robust design
- Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Slack redistribution for graceful degradation under voltage overscaling. 825-831 - Hassan Ebrahimi, Morteza Saheb Zamani
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. 832-837 - Hongbo Zhang, Martin D. F. Wong
On process-aware 1-D standard cell design. 838-842 - Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake:
D-A converter based variation analysis for analog layout design. 843-848
Emerging circuits and architectures
- Mona Arabzadeh, Mehdi Saeedi
Rule-based optimization of reversible circuits. 849-854 - Cihan Tunc
Variation tolerant logic mapping for crossbar array nano architectures. 855-860 - Marek A. Bawiec, Maciej Nikodem
Generalised threshold gate synthesis based on AND/OR/NOT representation of Boolean function. 861-866 - Masoud Rostami, Kartik Mohanram:
Novel dual-Vth independent-gate FinFET circuits. 867-872
System-level MPSoC analysis and optimization
- Shervin Sharifi, Ayse Kivilcim Coskun, Tajana Simunic Rosing:
Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs. 873-878 - Cathy Qun Xu, Chun Jason Xue
Energy efficient joint scheduling and multi-core interconnect design. 879-884 - Andreas Schranzhofer, Jian-Jia Chen
Dynamic and adaptive allocation of applications on MPSoC platforms. 885-890 - Raid Zuhair Ayoub, Tajana Simunic Rosing:
Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems. 891-896
Designers' forum: Embedded software development for multi-processor systems-on-chip
- Rainer Leupers, Jerónimo Castrillón:
MPSoC programming using the MAPS compiler. 897-902 - Gunar Schirner
System-level development of embedded software. 903-909
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