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Muhammad M. Khellah
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2020 – today
- 2023
- [c42]Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De:
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits 2023: 1-2 - 2021
- [j31]Ravi R. Iyer
, Vivek De
Advances in Microprocessor Cache Architectures Over the Last 25 Years. IEEE Micro 41(6): 78-88 (2021) - [j30]Saurabh Kumar
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2086-2097 (2021) - [c41]Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid
All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits 2021: 1-2 - 2020
- [j29]Suyoung Bang
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits 55(7): 1898-1908 (2020) - [c40]Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC 2020: 380-382 - [c39]Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits 2020: 1-2 - [c38]Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [c37]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j28]Pascal Andreas Meinerzhagen
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [c36]Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC 2019: 1-4 - [c35]Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019: 1-4 - 2018
- [j27]Keith A. Bowman
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 53(1): 3-7 (2018) - [c34]Thomas Burd, Muhammad M. Khellah, Byeong-Gyu Nam:
Session 2 overview: Processors: Digital architectures and systems subcommittee. ISSCC 2018: 32-33 - [c33]Pascal Meinerzhagen, Carlos Tokunaga
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [j26]Minki Cho
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52(1): 50-63 (2017) - [c32]Muhammad M. Khellah
Session 5 - Memory for emerging applications. CICC 2017: 1 - 2016
- [j25]Vijay Raghunathan, Muhammad M. Khellah
Recap of the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016). IEEE Des. Test 33(6): 93-94 (2016) - [j24]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - [c31]Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah
Synaptic sampling in hardware spiking neural networks. ISCAS 2016: 2090-2093 - [c30]Minki Cho, Stephen T. Kim, Carlos Tokunaga
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC 2016: 152-153 - [c29]Minki Cho, Carlos Tokunaga
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits 2016: 1-2 - 2015
- [c28]Minki Cho, Carlos Tokunaga
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. CICC 2015: 1-4 - [c27]Farah B. Yahya, Mohammad M. Mansour, James W. Tschanz, Muhammad M. Khellah
Designing low-VTh STT-RAM for write energy reduction in scaled technologies. ISQED 2015: 5-9 - [c26]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - [c25]Ahmed M. Ammar
A fully integrated charge sharing active decap scheme for power supply noise suppression. SoCC 2015: 374-379 - 2014
- [j23]Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 49(4): 917-927 (2014) - [c24]Carlos Tokunaga
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - [e1]Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra:
International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014. ACM 2014, ISBN 978-1-4503-2975-0 [contents] - 2012
- [c23]Minki Cho, Muhammad M. Khellah
Characterization of Inverse Temperature Dependence in logic circuits. CICC 2012: 1-4 - [c22]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c21]Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 - 2011
- [j22]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011) - [j21]Keith A. Bowman
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46(1): 194-208 (2011) - [j20]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46(4): 797-805 (2011) - [j19]Keith A. Bowman
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2017-2025 (2011) - 2010
- [j18]Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits 45(4): 751-758 (2010) - [c20]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c19]Keith A. Bowman
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 - [c18]Bibiche M. Geuskens, Muhammad M. Khellah
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC 2010: 1-4 - [c17]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 - [c16]James W. Tschanz, Keith A. Bowman
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 - [c15]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j17]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [j16]Muhammad M. Khellah
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44(4): 1199-1208 (2009) - [j15]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah
Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009) - [j14]DiaaEldin Khalil, Muhammad M. Khellah
SRAM dynamic stability estimation using MPFP and its applications. Microelectron. J. 40(11): 1523-1530 (2009) - [j13]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 384-394 (2009) - [j12]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2020-2032 (2009) - 2008
- [j11]Maged Ghoneima, Muhammad M. Khellah
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1904-1910 (2008) - [j10]D. E. Khalil, Muhammad M. Khellah
Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1639-1647 (2008) - [c14]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214 - [c13]DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah
Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 - [c12]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - 2007
- [j9]Muhammad M. Khellah
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [j8]Navid Azizi, Muhammad M. Khellah
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 746-757 (2007) - [j7]Maged Ghoneima
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007: 95402:1-95402:12 (2007) - 2006
- [j6]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 821-836 (2006) - [j5]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1928-1933 (2006) - [c11]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Reducing the data switching activity of serialized datastreams. ISCAS 2006 - [c10]Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De:
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006 - [c9]Keith A. Bowman
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 - [c8]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432 - [c7]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - 2005
- [c6]Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling. DAC 2005: 529-534 - [c5]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 - [c4]Muhammad M. Khellah
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257 - [c3]Yehea I. Ismail, Muhammad M. Khellah
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 - 2003
- [j4]Yibin Ye, Muhammad M. Khellah
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38(5): 839-842 (2003) - 2001
- [j3]Muhammad M. Khellah
A low-power high-performance current-mode multiport SRAM. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 590-598 (2001)
1990 – 1999
- 1998
- [c2]Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry:
A Low-Power High-Performance Embedded SRAM Macrocell. Great Lakes Symposium on VLSI 1998: 13-17 - [c1]Muhammad M. Khellah
Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. Great Lakes Symposium on VLSI 1998: 414-419 - 1996
- [j2]Stephen Dean Brown, Muhammad M. Khellah
Minimizing FPGA Interconnect Delays. IEEE Des. Test Comput. 13(4): 16-23 (1996) - [j1]Stephen Dean Brown, Muhammad M. Khellah
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. VLSI Design 4(4): 275-291 (1996)
Coauthor Index
Vivek De
aka: Vivek K. De
aka: Vivek K. De
[c42] [j31] [j30] [j29] [c40] [c39] [c38] [c37] [j28] [c36] [c35] [c33] [j26] [j24] [c30] [c29] [c28] [c26] [j23] [c24] [c22] [c21] [j22] [j21] [j20] [j19] [c20] [c19] [c18] [c17] [c16] [c15] [j17] [j16] [j14] [j13] [j12] [j11] [j10] [c13] [c12] [j9] [j8] [j7] [j6] [j5] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [j4]
Jaydeep P. Kulkarni
aka: Jaydeep Kulkarni
aka: Jaydeep Kulkarni
James W. Tschanz
aka: Jim Tschanz
aka: Jim Tschanz
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