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Yukio Mitsuyama
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2020 – today
- 2021
- [c26]Ryohei Yamamoto, Yuki Izumi, Ryo Aono, Takumi Nagahara, Tomonari Tanaka, Wang Liao, Yukio Mitsuyama:
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs. FPT 2021: 1-4 - 2020
- [j19]Yukio Mitsuyama, Takashi Asada, Makio Eguchi:
Measurement of Variations in FPGAs under Various Load Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 13: 39-41 (2020) - [c25]Wang Liao
, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS 2020: 1-5 - [c24]Masanori Hashimoto
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2019
- [c23]Tomonari Tanaka, Itsuki Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Yukio Mitsuyama:
Development of Autonomous Driving System Using Programmable SoCs. FPT 2019: 453-456 - 2018
- [j18]Hiroki Hihara
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j17]Hiroyuki Ochi
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [p1]Tomonori Izumi, Yukio Mitsuyama:
Design Flow and Design Tools. Principles and Structures of FPGAs 2018: 87-115 - 2016
- [c22]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - 2015
- [c21]Masanori Hashimoto
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - 2014
- [j16]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1461-1467 (2014) - [j15]Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1468-1482 (2014) - [j14]Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1483-1491 (2014) - [j13]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [c20]Yukio Mitsuyama, Hidetoshi Onodera:
Variability and Soft-Error Resilience in Dependable VLSI Platform. ATS 2014: 45-50 - 2013
- [j12]Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto
PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. IEICE Electron. Express 10(5): 20130081 (2013) - [j11]Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. IEICE Trans. Inf. Syst. 96-D(8): 1624-1631 (2013) - [j10]Takehiko Amaki, Masanori Hashimoto
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. IEEE Trans. Inf. Forensics Secur. 8(8): 1331-1342 (2013) - [j9]Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2165-2178 (2013) - [c19]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig 2013: 1-6 - 2012
- [j8]Hiroshi Fuketa, Masanori Hashimoto
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 333-343 (2012) - [c18]Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. FPL 2012: 615-618 - [c17]Dawood Alnajiar, Masanori Hashimoto
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig 2012: 1-7 - 2011
- [j7]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2545-2553 (2011) - [c16]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL 2011: 189-194 - [c15]Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS 2011: 152-161 - 2010
- [j6]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2417-2423 (2010) - [j5]Hiroshi Fuketa, Masanori Hashimoto
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1118-1129 (2010) - [c14]Hiroshi Fuketa, Masanori Hashimoto
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362 - [c13]Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED 2010: 646-651 - [c12]Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED 2010: 839-844 - [c11]Takehiko Amaki, Masanori Hashimoto
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA 2010: 107-121
2000 – 2009
- 2009
- [j4]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. 92-C(2): 281-285 (2009) - [j3]Hiroshi Fuketa, Masanori Hashimoto
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3094-3102 (2009) - [c10]Hiroshi Fuketa, Masanori Hashimoto
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271 - [c9]Hiroshi Fuketa, Masanori Hashimoto
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218 - [c8]Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192 - [c7]Koichi Hamamoto, Masanori Hashimoto
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED 2009: 51-56 - 2008
- [j2]Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto
Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3651-3662 (2008) - [c6]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390 - [c5]Hiroshi Fuketa, Masanori Hashimoto
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8 - 2005
- [j1]Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa:
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 899-906 (2005) - 2002
- [c4]Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
Burst mode: a new acceleration mode for 128-bit block ciphers. CICC 2002: 151-154 - 2001
- [c3]Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
A dynamically reconfigurable hardware-based cipher chip. ASP-DAC 2001: 11-12 - [c2]Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
VLSI architecture of dynamically reconfigurable hardware-based cipher. ISCAS (4) 2001: 734-737
1990 – 1999
- 1999
- [c1]Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng:
FeRAM Circuit Technology for System on a Chip. Evolvable Hardware 1999: 193-
Coauthor Index
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