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Yi-Chang Lu
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2020 – today
- 2024
- [c60]Hung-Yu Shu, Yi-Hsien Lin, Yi-Chang Lu:
Deep Plug-and-play Nighttime Non-blind Deblurring with Saturated Pixel Handling Schemes. WACV 2024: 1527-1535 - 2022
- [j9]Chih-Hsiang Yang
, Yi-Hsien Lin
A Variation-Based Nighttime Image Dehazing Flow With a Physically Valid Illumination Estimator and a Luminance-Guided Coloring Model. IEEE Access 10: 50153-50166 (2022) - [j8]Yang-Ming Yeh
MSRCall: a multi-scale deep neural network to basecall Oxford Nanopore sequences. Bioinform. 38(16): 3877-3884 (2022) - [j7]Yi-Hsien Lin
Low-Light Enhancement Using a Plug-and-Play Retinex Model With Shrinkage Mapping for Illumination Estimation. IEEE Trans. Image Process. 31: 4897-4908 (2022) - [c59]Chuan-Yu Chen, Shih-Hao Huang, Yi-Chang Lu:
A Hardware Accelerator for Long Sequence Alignment with the Bit-Vector Scoring Scheme and Divide-and-Conquer Traceback. BioCAS 2022: 467-471 - [c58]Hao-Wei Liu, Zhe-Wei Shen, Yang-Ming Yeh, Yi-Chang Lu:
A Nucleotide-Position-Based Data Format for Fast Variant Calling and Its Hardware Analyzer Design. BioCAS 2022: 529-533 - [c57]Bo-Fan Chen, Yang-Ming Yeh, Yi-Chang Lu:
CF-Net: Complementary Fusion Network for Rotation Invariant Point Cloud Completion. ICASSP 2022: 2275-2279 - [c56]Shih-Wei Hsieh, Chih-Hsiang Yang, Yi-Chang Lu:
Shadow Removal Through Learning-Based Region Matching and Mapping Function Optimization. ICME 2022: 1-6 - [c55]Shih-Shiuan Weng, Yang-Ming Yeh, Yu-Cheng Li, Yi-Chang Lu:
An Alignment-Based Hardware Accelerator for Rapid Prediction of RNA Secondary Structures. ISCAS 2022: 2700-2704 - 2021
- [c54]Sheng-Jui Huang, Yi-Hsien Lin, Chi-Hung Weng, Yi-Chang Lu:
A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping. APCCAS 2021: 69-72 - [c53]Yu-Chen Chou, Yen-Po Lin, Yang-Ming Yeh, Yi-Chang Lu:
3D-GFE: a Three-Dimensional Geometric-Feature Extractor for Point Cloud Data. APSIPA ASC 2021: 2013-2017 - [c52]Yen-Po Lin, Yang-Ming Yeh, Yu-Chen Chou, Yi-Chang Lu:
Attention EdgeConv For 3D Point Cloud Classification. APSIPA ASC 2021: 2018-2022 - [c51]Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen:
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE 2021: 1799-1802 - [c50]Jing-Ping Wu, Yi-Chien Lin
A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. ISCAS 2021: 1-4 - [c49]Fang-Tsung Hsiao, Yi-Hsien Lin, Yi-Chang Lu:
Using Regularity Unit As Guidance For Summarization-Based Image Resizing. VCIP 2021: 1-5 - [i1]Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu:
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. CoRR abs/2102.03045 (2021) - 2020
- [c48]Yu-Cheng Li, Mao-Jan Lin, Xiao-Xuan Huang, Chien-Yu Chen, Yi-Chang Lu:
Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions. BIBE 2020: 23-28 - [c47]Chia-Han Huang, Yi-Chang Lu:
An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior. ISCAS 2020: 1-5 - [c46]Cheng-Yeh Liou, Cheng-Yen Chuang, Chia-Han Huang, Yi-Chang Lu:
HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain. VCIP 2020: 499-502 - [c45]Chi-Yun Yang, Yang-Ming Yeh, Yi-Chang Lu:
Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data. VLSI-DAT 2020: 1-3
2010 – 2019
- 2019
- [j6]Yu-Cheng Li, Yi-Chang Lu
BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment. IEEE Trans. Biomed. Circuits Syst. 13(6): 1771-1782 (2019) - [c44]Ming-Hung Chen
Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design. BIBE 2019: 563-566 - [c43]Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks. BioCAS 2019: 1-4 - [c42]Ching-Fan Chiang, Yang-Ming Yeh
Colorization of High-Frame-Rate Monochrome Videos Using Synchronized Low-Frame-Rate Color Data. CCIW 2019: 276-285 - [c41]Man-Rong Chen, Hao-Wei Liu, Yi-Hsien Lin, Yi-Chang Lu
A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data. ISCAS 2019: 1-5 - 2018
- [c40]Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen
Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator. ASAP 2018: 1-9 - [c39]Chien-An Wang, Sheng-Jui Huang, Yu-Cheng Li, Yi-Chang Lu
An FPGA-Based Liquid Association Calculator for Genome-Wide Co-Expression Analysis. DSP 2018: 1-4 - [c38]Shih-Wei Hsieh, Yao-Cheng Yang, Chi-Ming Yeh, Sheng-Jui Huang, Yi-Chang Lu
Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. ICIP 2018: 395-399 - [c37]Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu:
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. ISCAS 2018: 1-4 - [c36]Po-Hsiang Hsu, Yang-Ming Yeh
A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. ISCAS 2018: 1-5 - [c35]Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen
A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. ISCAS 2018: 1-5 - [c34]Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu
Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment. NORCAS 2018: 1-5 - 2017
- [c33]Ya-Fang Shih, Yang-Ming Yeh
Deep Co-occurrence Feature Learning for Visual Object Recognition. CVPR 2017: 7302-7311 - 2016
- [c32]Chun-Shen Liu, Nae-Chyun Chen
An FPGA-based quality filter for de novo sequence assembly pipeline. APCCAS 2016: 139-142 - [c31]Xiao-Xuan Huang, Chun-Hsien Ho, Yu-Cheng Li, Nae-Chyun Chen
Step shift: A fast image segmentation algorithm and its hardware implementation for next-generation sequencing fluorescence data. APCCAS 2016: 202-205 - [c30]Che-Wei Chang, Min-Hung Chen, Kuan-Chang Chen, Chi-Ming Yeh, Yi-Chang Lu
Mask design for pinhole-array-based hand-held light field cameras with applications in depth estimation. APSIPA 2016: 1-4 - [c29]Yi-Hsiang Chen, Nae-Chyun Chen
Queue-based segmentation algorithm for refining depth maps in light field camera applications. GCCE 2016: 1-2 - [c28]Yu-Hsiang Kao, Sheng-Jui Huang, Yi-Chang Lu
An iterative re-weighted least squares processor design for deblurring parabolic camera images. GCCE 2016: 1-2 - [c27]Yang-Ming Yeh
An orthogonal matching pursuit processor for sparse-representation-based light field data compression. GCCE 2016: 1-2 - [c26]Lu Xiao, Xiao-Xuan Huang, Yi-Chang Lu
Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation. ISOCC 2016: 327-328 - [c25]Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen
A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit method. NORCAS 2016: 1-5 - 2015
- [c24]Nae-Chyun Chen
Power efficient special processor design for burrows-wheeler-transform-based short read sequence alignment. BioCAS 2015: 1-4 - [c23]Yi-Jung Chen, Chia-Lin Yang
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS 2015: 430-436 - 2014
- [j5]Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 667-674 (2014) - [c22]Min-Hung Chen, Ching-Fan Chiang, Yi-Chang Lu
Depth estimation for hand-held light field cameras under low light conditions. IC3D 2014: 1-4 - [c21]Che-Wei Chang, Man-Rong Chen, Po-Hsiang Hsu, Yi-Chang Lu
A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data. ISCAS 2014: 786-789 - 2013
- [j4]Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu
LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems. IEEE Signal Process. Lett. 20(7): 645-648 (2013) - [c20]Chi-Kai Shen, Yi-Chang Lu
Power distribution network modeling for 3-D ICs with TSV arrays. ASP-DAC 2013: 17-22 - [c19]Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu
Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium 2013: 43-48 - [c18]Yuan-Hsiang Kuo, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. ICASSP 2013: 1158-1161 - [c17]Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED 2013: 304 - [c16]Chin-Khai Tang, Yi-Chang Lu
A power-efficient asynchronous circuit style with selective input-channel restoring. MWSCAS 2013: 25-28 - [c15]Yu-Long Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
Architecture and circuit design of parallel processing elements for de novo sequence assembly. SoCC 2013: 50-54 - [c14]Shih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu
Light field data processor design for depth estimation using confidence-assisted disparities. SoCC 2013: 129-133 - [c13]Chun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu
Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data. SoCC 2013: 134-138 - [c12]Hitoshi Mizunuma, Yi-Chang Lu
Thermal coupling aware task migration using neighboring core search for many-core systems. VLSI-DAT 2013: 1-4 - 2011
- [j3]Hitoshi Mizunuma, Yi-Chang Lu
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1293-1306 (2011) - 2010
- [c11]Yong-Ruei Huang, Jia-Hong Pan, Yi-Chang Lu
Thermal-aware router-sharing architecture for 3D Network-on-Chip designs. APCCAS 2010: 1087-1090 - [c10]Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. ASP-DAC 2010: 651-656 - [c9]Chih-Chieh Chen, Yi-Chang Lu
Light field based digital refocusing using a DSLR camera with a pinhole array mask. ICASSP 2010: 754-757 - [c8]Chih-Chieh Chen, Shih-Chieh Fan Chiang, Xiao-Xuan Huang, Ming-Shing Su, Yi-Chang Lu
Depth estimation of light field data from pinhole-masked DSLR cameras. ICIP 2010: 1769-1772
2000 – 2009
- 2009
- [c7]Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD 2009: 256-263 - 2008
- [c6]Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. ICCAD 2008: 286-291 - [c5]Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu
An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. ISQED 2008: 769-773 - 2007
- [j2]Mingjie Lin, Abbas El Gamal, Yi-Chang Lu
Performance Benefits of Monolithically Stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 216-229 (2007) - [j1]Cosmin Iorga, Yi-Chang Lu
A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications. IEEE Trans. Instrum. Meas. 56(6): 2330-2337 (2007) - 2006
- [c4]Mingjie Lin, Abbas El Gamal, Yi-Chang Lu
Performance benefits of monolithically stacked 3D-FPGA. FPGA 2006: 113-122 - 2004
- [c3]Georgios Veronis, Yi-Chang Lu
Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. ISQED 2004: 303-308 - 2001
- [c2]Yi-Chang Lu
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC 2001: 241-244 - [c1]Yi-Chang Lu
Min/max On-Chip Inductance Models and Delay Metrics. DAC 2001: 341-346
Coauthor Index
aka: Yu-Cheng Li
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