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Aditya Yanamandra
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2010 – 2019
- 2011
- [j2]Asit K. Mishra, Aditya Yanamandra, Reetuparna Das
, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71(5): 625-640 (2011) - 2010
- [j1]Chrysostomos Nicopoulos
On the Effects of Process Variation in Network-on-Chip Architectures. IEEE Trans. Dependable Secur. Comput. 7(3): 240-254 (2010) - [c6]Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan:
Optimizing power and performance for reliable on-chip networks. ASP-DAC 2010: 431-436
2000 – 2009
- 2009
- [c5]Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan:
In-Network Caching for Chip Multiprocessors. HiPEAC 2009: 373-388 - [c4]Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin:
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. NANOARCH 2009: 51-56 - 2008
- [c3]Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos
Analysis and solutions to issue queue process variation. DSN 2008: 11-21 - [c2]Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim:
A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 - [c1]Aditya Yanamandra, Bryan Cover, Padma Raghavan, Mary Jane Irwin, Mahmut T. Kandemir:
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations. IPDPS 2008: 1-10
Coauthor Index
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