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Yuan-Kai Ho
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2010 – 2019
- 2014
- [j2]Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang
, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen:
Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 224-236 (2014) - 2013
- [j1]Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang
Escape Routing for Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1347-1356 (2013) - [c6]Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang
Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC 2013: 187-192 - [c5]Yuan-Kai Ho, Yao-Wen Chang
Multiple chip planning for chip-interposer codesign. DAC 2013: 27:1-27:6 - 2012
- [c4]Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang
Obstacle-avoiding free-assignment routing for flip-chip designs. DAC 2012: 1088-1093 - 2011
- [c3]Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang
Escape routing for staggered-pin-array PCBs. ICCAD 2011: 306-309 - 2010
- [c2]Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. ASP-DAC 2010: 395-400
2000 – 2009
- 2008
- [c1]Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu:
Type-matching clock tree for zero skew clock gating. DAC 2008: 714-719
Coauthor Index
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