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Xin Zhao 0001
Person information
- affiliation: Georgia Institute of Technology, Atlanta, GA, USA
Other persons with the same name
- Xin Zhao — disambiguation page
- Xin Zhao 0002 — University of New South Wales, Sydney, Australia
- Xin Zhao 0003
— Tencent, Palo Alto, CA, USA (and 2 more)
- Xin Zhao 0004
- Xin Zhao 0005
- Xin Zhao 0006
- Xin Zhao 0007
- Xin Zhao 0008
- Xin Zhao 0009
- Xin Zhao 0010
- Xin Zhao 0011
- Xin Zhao 0012
- Xin Zhao 0013
- Xin Zhao 0014
- Xin Zhao 0015 — Stony Brook University, Computer Science Department, NY, USA
- Xin Zhao 0016 — University of Michigan, USA
- Xin Zhao 0017 — University of Lille, France
- Wayne Xin Zhao
- Xin Zhao 0019
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2010 – 2019
- 2015
- [j4]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - 2013
- [c16]Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. ASP-DAC 2013: 693-698 - [c15]Xin Zhao, Yang Wan, Michael Scheuermann, Sung Kyu Lim
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs. ICCAD 2013: 363-370 - 2012
- [b1]Xin Zhao:
Reliable clock and power delivery network design for three-dimensional integrated circuits. Georgia Institute of Technology, Atlanta, GA, USA, 2012 - [j3]Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim
Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1222-1234 (2012) - [c14]Xin Zhao, Sung Kyu Lim
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. ASP-DAC 2012: 347-352 - [c13]Xin Zhao, Michael Scheuermann, Sung Kyu Lim
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. DAC 2012: 157-162 - [c12]Xin Zhao, Sung Kyu Lim
TSV array utilization in low-power 3D clock network design. ISLPED 2012: 21-26 - [c11]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - 2011
- [j2]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 732-745 (2011) - [j1]Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1349-1358 (2011) - [c10]Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626 - [c9]Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD 2011: 90-95 - [c8]Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim:
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. ISLPED 2011: 9-14 - 2010
- [c7]Xin Zhao, Sung Kyu Lim
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. ASP-DAC 2010: 175-180 - [c6]Krit Athikulwongse, Xin Zhao, Sung Kyu Lim
Buffered clock tree sizing for skew minimization under power and thermal budgets. ASP-DAC 2010: 474-479 - [c5]Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4
2000 – 2009
- 2009
- [c4]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
Pre-bond testable low-power clock tree design for 3D stacked ICs. ICCAD 2009: 184-190 - [c3]Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim
Slew-aware clock tree design for reliable subthreshold circuits. ISLPED 2009: 15-20 - 2008
- [c2]Jacob R. Minz, Xin Zhao, Sung Kyu Lim
Buffered clock tree synthesis for 3D ICs under thermal variations. ASP-DAC 2008: 504-509 - 2007
- [c1]Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. ASP-DAC 2007: 547-552
Coauthor Index
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