research-article

On process-aware 1-D standard cell design

Authors:

Hongbo Zhang,

Martin D. F. Wong,

Kai-Yuan ChaoAuthors Info & Claims

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Pages 838 - 842

Published: 18 January 2010 Publication History

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Abstract

When VLSI technology scales down to sub-40nm process node, systematic variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1--D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE).

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Cited By

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Vidal-Obiols ACortadella JPetit JBehjat LHan JVelev MChen D(2017)Under-the-Cell Routing to Improve ManufacturabilityProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060428(125-130)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060428
Liu HHan TChen Y(2016)Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errorsMicroelectronic Engineering10.1016/j.mee.2016.03.048155:C(107-113)Online publication date: 2-Apr-2016
https://dl.acm.org/doi/10.1016/j.mee.2016.03.048
Ye WYu BPan DBan YLiebmann LJones ALi HCoskun AMargala M(2015)Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-LineProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742084(289-294)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742084
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Information & Contributors

Information

Published In

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

January 2010

920 pages

ISBN:9781605588377

General Chair:
Youn-Long Lin
National Tsing Hua University

Publisher

IEEE Press

Publication History

Published: 18 January 2010

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Research-article

Conference

ASPDAC '10

Sponsor:

TICD
SIGDA

ASPDAC '10: Asia and South Pacific Design Automation Conference

January 18 - 21, 2010

Taipei, Taiwan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

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Vidal-Obiols ACortadella JPetit JBehjat LHan JVelev MChen D(2017)Under-the-Cell Routing to Improve ManufacturabilityProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060428(125-130)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060428
Liu HHan TChen Y(2016)Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errorsMicroelectronic Engineering10.1016/j.mee.2016.03.048155:C(107-113)Online publication date: 2-Apr-2016
https://dl.acm.org/doi/10.1016/j.mee.2016.03.048
Ye WYu BPan DBan YLiebmann LJones ALi HCoskun AMargala M(2015)Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-LineProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742084(289-294)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742084
Zhang HDeng YKye JWong M(2012)Impact of lithography retargeting process on low level interconnect in 20nm technologyProceedings of the International Workshop on System Level Interconnect Prediction10.1145/2347655.2347659(3-10)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2347655.2347659
Zhang HDu YWong MChao K(2011)Mask cost reduction with circuit performance consideration for self-aligned double patterningProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950965(787-792)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950965

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Legalization algorithm for multiple-row height standard cell design

Routability driven white space allocation for fixed-die standard-cell placement

Triple patterning lithography aware optimization for standard cell based design