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Jun Seomun
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2010 – 2019
- 2013
- [c7]Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker
, Subhasish Mitra
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. CICC 2013: 1-4 - [c6]Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra
Early-life-failure detection using SAT-based ATPG. ITC 2013: 1-10 - 2012
- [j5]Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 391-403 (2012) - [j4]Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin:
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1885-1890 (2012) - [c5]Chungki Oh, Hyung-Ock Kim, Jun Seomun, Wook Kim, Jaehan Jeon, Kyung Tae Do, Hyo-Sig Won, Kee Sup Kim:
Thermal-aware body bias modulation for high performance mobile core. ISOCC 2012: 147-150 - 2011
- [j3]Jun Seomun, Youngsoo Shin:
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 227-236 (2011) - 2010
- [j2]Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai:
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4): 28:1-28:37 (2010) - [c4]Jun Seomun, Seungwhun Paik, Youngsoo Shin:
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC 2010: 581-586 - [c3]Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis and implementation of active mode power gating circuits. DAC 2010: 487-492
2000 – 2009
- 2009
- [c2]Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han
Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126 - 2008
- [j1]Jun Seomun, Jae-Hyun Kim, Youngsoo Shin:
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1956-1968 (2008) - 2007
- [c1]Jun Seomun, Jaehyun Kim, Youngsoo Shin:
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. DAC 2007: 103-106
Coauthor Index
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