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Kuan-Hsien Ho
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2020 – today
- 2022
- [c9]Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956
2010 – 2019
- 2015
- [j4]Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang
, Hui-Fang Tsao:
Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 161-172 (2015) - 2014
- [c8]Kuan-Hsien Ho, Yao-Wen Chang
A New Asynchronous Pipeline Template for Power and Performance Optimization. DAC 2014: 204:1-204:6 - 2013
- [c7]Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. DAC 2013: 6:1-6:6 - 2012
- [j3]Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1723-1733 (2012) - [c6]Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang:
Clock rescheduling for timing engineering change orders. ASP-DAC 2012: 517-522 - [c5]Gwo-Ruey Yu, Kuan-Hsien Ho:
Constraints on control input and output of polynomial fuzzy systems via a sum of squares approach. FUZZ-IEEE 2012: 1-6 - 2010
- [j2]Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 697-710 (2010) - [c4]Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang
TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336 - [c3]Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. ICCAD 2010: 452-457
2000 – 2009
- 2009
- [j1]Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2): 31:1-31:17 (2009) - 2008
- [c2]Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang
Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517 - 2007
- [c1]Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379
Coauthor Index
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