research-article

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

Authors:

Sung Kyu LimAuthors Info & Claims

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Pages 175 - 180

Published: 18 January 2010 Publication History

Abstract

In this paper, three effective design techniques are presented to effectively reduce the clock power consumption and slew of the 3D clock distribution network: (1) controlling the bound of through-silicon-vias (TSVs) used in between adjacent dies, (2) controlling the maximum load capacitance of the clock buffer, (3) adjusting the clock source location in the 3D stack. We discuss how these design factors affect the overall wirelength, clock power, slew, skew, and routing congestion in the practical 3D clock network design. SPICE simulation indicates that: (1) a 3D clock tree with multiple TSVs achieves up to 31% power saving, 52% wirelength saving and better slew control as compared with the single-TSV case; (2) by placing the clock source on the middle die in the 3D stack, an additional 7.7% power savings, 9.2% wirelength savings, and 33% TSV savings are obtained compared with the clock source on the topmost die. This work aims at helping designers construct reliable low-power and low-slew 3D clock network by making the right decisions on TSV usage, clock buffer insertion, and clock source placement.

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Cited By

Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Todri-Sanial ACheng Y(2016)A Study of 3-D Power Delivery Networks With Multiple Clock DomainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254927524:11(3218-3231)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2549275
Knechtel JMarkov ILienig JThiele MHu A(2012)Multiobjective optimization of deadspace, a critical resource for 3D-IC integrationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429538(705-712)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429538
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Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
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Published In

cover image ACM Conferences

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

January 2010

920 pages

ISBN:9781605588377

General Chair:
Youn-Long Lin
National Tsing Hua University

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TICD: TICD
SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS

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IEEE Press

Publication History

Published: 18 January 2010

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ASPDAC '10

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TICD
SIGDA

ASPDAC '10: Asia and South Pacific Design Automation Conference

January 18 - 21, 2010

Taipei, Taiwan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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January 20 - 23, 2025

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Cited By

Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Todri-Sanial ACheng Y(2016)A Study of 3-D Power Delivery Networks With Multiple Clock DomainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254927524:11(3218-3231)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2549275
Knechtel JMarkov ILienig JThiele MHu A(2012)Multiobjective optimization of deadspace, a critical resource for 3D-IC integrationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429538(705-712)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429538
Xu HPavlidis VDe Micheli G(2012)Effect of process variations in 3D global clock distribution networksACM Journal on Emerging Technologies in Computing Systems10.1145/2287696.22877038:3(1-25)Online publication date: 15-Aug-2012
https://dl.acm.org/doi/10.1145/2287696.2287703
Chen FHwang TGroeneveld PSciuto DHassoun S(2012)Clock tree synthesis with methodology of re-use in 3D ICProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228559(1094-1099)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228559
Kim TKim T(2011)Clock Tree synthesis for TSV-based 3D IC designsACM Transactions on Design Automation of Electronic Systems10.1145/2003695.200370816:4(1-21)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003708
Xu HPavlidis VDe Micheli GReda SWang J(2010)Process-induced skew variation for scaled 2-D and 3-D ICsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811107(17-24)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811107

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