research-article

ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

Authors:

Andrew B. Kahng,

Kambiz SamadiAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 423 - 428

Published: 20 April 2009 Publication History

Abstract

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -- the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -- we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

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Information

Published In

cover image ACM Conferences

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

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DATE '09

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Jiang FLi CChen LLiu JZhang WXu JKim T(2024)SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power GatingProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473870(13-18)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473870
Li FWang YLiu CLi HLi XBolchini CO'Connor IVerbauwhede IWille R(2022)NoCeptionProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540084(1035-1040)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540084
Joseph JBamberg LHajjar IPerjikolaei BGarcía-Ortiz APionteck T(2021)Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCsACM Transactions on Modeling and Computer Simulation10.1145/347275432:1(1-21)Online publication date: 27-Sep-2021
https://dl.acm.org/doi/10.1145/3472754
Deb DJose JPalesi M(2020)COPEACM Transactions on Design Automation of Electronic Systems10.1145/342814926:3(1-31)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3428149
Wang KLouri AKaranth ABunescu RManne SHunter HAltman E(2019)IntelliNoCProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322274(589-600)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322274
von Kistowski JGrohmann JSchmitt NKounev SApte VDi Marco ALitoiu MMerseguer J(2019)Predicting Server Power Consumption from Standard Rating ResultsProceedings of the 2019 ACM/SPEC International Conference on Performance Engineering10.1145/3297663.3310298(301-312)Online publication date: 4-Apr-2019
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Lee MCui YSomu TLuo TZhou JTang WWong WGoh R(2019)A System-Level Simulator for RRAM-Based Neuromorphic Computing ChipsACM Transactions on Architecture and Code Optimization10.1145/329105415:4(1-24)Online publication date: 8-Jan-2019
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Bhanu PKulkarni PJ S(2019)Fault-Tolerant Network-on-Chip Design with Flexible Spare Core PlacementACM Journal on Emerging Technologies in Computing Systems10.1145/326998315:1(1-23)Online publication date: 14-Jan-2019
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Das ABabu SJose JJose SPalesi MLu ZVangal SXu JBogdan P(2018)Critical packet prioritisation by slack-aware re-routing in on-chip networksProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306631(1-8)Online publication date: 4-Oct-2018
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Bontupalli VYakopcic CHasan RTaha T(2018)Efficient Memristor-Based Architecture for Intrusion Detection and High-Speed Packet ClassificationACM Journal on Emerging Technologies in Computing Systems10.1145/326481914:4(1-27)Online publication date: 28-Nov-2018
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