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Orion: a power-performance simulator for interconnection networks

Published: 18 November 2002 Publication History

Abstract

With the prevalence of server blades and systems-on-a-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limited tool support available for their design. While performance simulators have been built that enable performance estimation while varying network parameters, these cover only one metric of interest in modern designs. System power consumption is increasingly becoming equally, if not more important than performance. It is now critical to get detailed power-performance tradeoff information early in the microarchitectural design cycle. This is especially so as interconnection networks consume a significant fraction of total system power. It is exactly this gap that the work presented in this paper aims to fill.We present Orion, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power-performance trade-offs at the architectural-level. This capability is provided within a general framework that builds a simulator starting from a microarchitectural specification of the interconnection network. A key component of this construction is the architectural-level parameterized power models that we have derived as part of this effort. Using component power models and a synthesized efficient power (and performance) simulator, a microarchitect can rapidly explore the design space. As case studies, we demonstrate the use of Orion in determining optimal system parameters, in examining the effect of diverse traffic conditions, as well as evaluating new network microarchitectures. In each of the above, the ability to simultaneously monitor power and performance is key in determining suitable microarchitectures.

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cover image ACM Conferences
MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
November 2002
442 pages
ISBN:0769518591

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IEEE Computer Society Press

Washington, DC, United States

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Published: 18 November 2002

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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  • (2018)Utility Aware Snoozy Caches for Energy Efficient Chip Multi-ProcessorsProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194581(249-254)Online publication date: 30-May-2018
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