The design and use of simplepower: a cycle-accurate energy estimation tool
W Ye, N Vijaykrishnan, M Kandemir… - Proceedings of the 37th …, 2000 - dl.acm.org
Proceedings of the 37th Annual Design Automation Conference, 2000•dl.acm.org
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower,
for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on
energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses
transition sensitive energy models forms the cornerstone of this framework. SimplePower
also pro vides the energy consumed in the memory system and on-chip buses using
analytical energy models. We presen t the use of SimplePower to evaluate the impact of a …
for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on
energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses
transition sensitive energy models forms the cornerstone of this framework. SimplePower
also pro vides the energy consumed in the memory system and on-chip buses using
analytical energy models. We presen t the use of SimplePower to evaluate the impact of a …
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models.
We presen t the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively.