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ORION 2.0: A Power-Area Simulator for Interconnection Networks

Published: 01 January 2012 Publication History

Abstract

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.

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  • (2022)A Survey on Memory-centric Computer ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/354497418:4(1-50)Online publication date: 25-Oct-2022
  • (2022)Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoCACM Transactions on Embedded Computing Systems10.1145/352024121:4(1-29)Online publication date: 23-Aug-2022
  • (2022)Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon EraACM Journal on Emerging Technologies in Computing Systems10.1145/350177118:3(1-18)Online publication date: 22-Mar-2022
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Information & Contributors

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 20, Issue 1
January 2012
200 pages

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 January 2012

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Cited By

View all
  • (2022)A Survey on Memory-centric Computer ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/354497418:4(1-50)Online publication date: 25-Oct-2022
  • (2022)Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoCACM Transactions on Embedded Computing Systems10.1145/352024121:4(1-29)Online publication date: 23-Aug-2022
  • (2022)Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon EraACM Journal on Emerging Technologies in Computing Systems10.1145/350177118:3(1-18)Online publication date: 22-Mar-2022
  • (2022)Power efficient network selector placement in control plane of multiple networks-on-chipThe Journal of Supercomputing10.1007/s11227-021-04098-478:5(6664-6695)Online publication date: 1-Apr-2022
  • (2021)Distributed Graph Processing System and Processing-in-memory Architecture with Precise Loop-carried Dependency GuaranteeACM Transactions on Computer Systems10.1145/345368137:1-4(1-37)Online publication date: 1-Jul-2021
  • (2021)FreqCounterJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102252119:COnline publication date: 1-Oct-2021
  • (2021)3D-TTN: a power efficient cost effective high performance hierarchical interconnection network for next generation green supercomputerCluster Computing10.1007/s10586-021-03297-124:4(2897-2908)Online publication date: 1-Dec-2021
  • (2020)A Congestion Controlled and Load Balanced Selection Strategy for Networks on ChipInternational Journal of Distributed Systems and Technologies10.4018/IJDST.202001010111:1(1-14)Online publication date: 1-Jan-2020
  • (2020)GPUOPTACM Journal on Emerging Technologies in Computing Systems10.1145/341685017:1(1-26)Online publication date: 22-Sep-2020
  • (2019)Predict, Share, and Recycle Your Way to Low-power Nanophotonic NetworksACM Journal on Emerging Technologies in Computing Systems10.1145/335658516:1(1-26)Online publication date: 15-Oct-2019
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