research-article

Niagara: A 32-Way Multithreaded Sparc Processor

Authors:

Poonacha Kongetira,

Kathirgamar Aingaran,

Kunle OlukotunAuthors Info & Claims

IEEE Micro, Volume 25, Issue 2

Pages 21 - 29

https://doi.org/10.1109/MM.2005.35

Published: 01 March 2005 Publication History

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Abstract

The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.

References

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S.R. Kunkel, et al., "A Performance Methodology for Commercial Servers," IBM J. Research and Development, vol. 44, no. 6, 2000, pp. 851-872.

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L. Barroso J. Dean and U. Hoezle, "Web Search for a Planet: The Architecture of the Google Cluster," IEEE Micro, vol 23, no. 2, Mar.-Apr. 2003, pp. 22-28.

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K. Olukotun, et al., "The Case for a Single Chip Multiprocessor," Proc. 7<sup>th</sup> Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), 1996, pp. 2-11.

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J. Laudon A. Gupta and M. Horowitz, "Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations," Proc. 6th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VI), ACM Press, 1994, pp. 308-316.

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S. Kapil H. McGhan and J. Lawrendra, "A Chip Multithreaded Processor for Network-Facing Workloads," IEEE Micro, vol. 24, no. 2, Mar.-Apr. 2004, pp. 20-30.

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J. Hart, et al., "Implementation of a 4th-Generation 1.8 GHz Dual Core Sparc V9 Microprocessor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, http://www.isscc.org/isscc/2005/ap/ISSCC2005AdvanceProgram.pdf.

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Cited By

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Gupta NVaisla KKumar R(2021)Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine LearningSN Computer Science10.1007/s42979-021-00766-72:5Online publication date: 10-Jul-2021
https://dl.acm.org/doi/10.1007/s42979-021-00766-7
Leidel JWang XWilliams BChen Y(2020)Toward a Microarchitecture for Efficient Execution of Irregular ApplicationsACM Transactions on Parallel Computing10.1145/34180827:4(1-24)Online publication date: 27-Sep-2020
https://dl.acm.org/doi/10.1145/3418082
Chen CXiang XLiu CShang YGuo RLiu DLu YHao ZLuo JChen ZLi CPu YMeng JYan XXie YQi XMartínez JDuato JEeckhout L(2020)Xuantie-910Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00016(52-64)Online publication date: 30-May-2020
https://dl.acm.org/doi/10.1109/ISCA45697.2020.00016
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Index Terms

Niagara: A 32-Way Multithreaded Sparc Processor
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

IEEE Micro Volume 25, Issue 2

March 2005

65 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 March 2005

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Gupta NVaisla KKumar R(2021)Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine LearningSN Computer Science10.1007/s42979-021-00766-72:5Online publication date: 10-Jul-2021
Leidel JWang XWilliams BChen Y(2020)Toward a Microarchitecture for Efficient Execution of Irregular ApplicationsACM Transactions on Parallel Computing10.1145/34180827:4(1-24)Online publication date: 27-Sep-2020
Chen CXiang XLiu CShang YGuo RLiu DLu YHao ZLuo JChen ZLi CPu YMeng JYan XXie YQi XMartínez JDuato JEeckhout L(2020)Xuantie-910Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00016(52-64)Online publication date: 30-May-2020
Silva LFerreira RCanesche MMenezes MVieira MPenha JJamieson PNacif J(2019)READYACM Transactions on Embedded Computing Systems10.1145/335818718:5s(1-20)Online publication date: 7-Oct-2019
Zahran M(2019)Heterogeneous ComputingundefinedOnline publication date: 1-Mar-2019
Jia ZZlateski ADurand FLi K(2018)Optimizing N-dimensional, winograd-based convolution for manycore CPUsACM SIGPLAN Notices10.1145/3200691.317849653:1(109-123)Online publication date: 10-Feb-2018
Jia ZZlateski ADurand FLi KKrall AGross T(2018)Optimizing N-dimensional, winograd-based convolution for manycore CPUsProceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3178487.3178496(109-123)Online publication date: 10-Feb-2018
Shen DChabbi MLiu X(2018)An Evaluation of Vectorization and Cache Reuse Tradeoffs on Modern CPUsProceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/3178442.3178445(21-30)Online publication date: 24-Feb-2018
Gandhi ADube PKarve AKochut AZhang L(2018)Model-driven optimal resource scaling in cloudSoftware and Systems Modeling (SoSyM)10.1007/s10270-017-0584-y17:2(509-526)Online publication date: 1-May-2018
Leidel JWang XChen Y(2017)Pressure-Driven Hardware Managed Thread Concurrency for Irregular ApplicationsProceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms10.1145/3149704.3149705(1-8)Online publication date: 12-Nov-2017
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CSMT: Simultaneous Multithreading for Clustered VLIW Processors

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm

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