Article

Route packets, not wires: on-chip inteconnection networks

Authors:

William J. Dally,

Brian TowlesAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 684 - 689

https://doi.org/10.1145/378239.379048

Published: 22 June 2001 Publication History

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Abstract

Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.

References

[1]

"The CoreConnect TM Bus Architecture" IBM, 1999, http://www.chips.ibm.com/products/coreconnect/docs/crcon_wp.pdf.

Google Scholar

[2]

DALLY,WILLIAM J., "Virtual Channel Flow Control." IEEE Transactions on Parallel and Distributed Systems, March 1992, pp. 194-205.

Digital Library

Google Scholar

[3]

DALLY,WILLIAM J., AND POULTON,JOHN W., Digital Systems Engineering, Cambridge University Press, 1998.

Digital Library

Google Scholar

[4]

MIZUNO,MASAYUKI AND DALLY,WILLIAM J., "Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data," 2001 ISSCC, February, 2001, pp. 346-347.

Google Scholar

[5]

"Open Core Protocol TM Data Sheet" Sonics, Inc., http://www.sonicsinc.com/Documents/OpenCoreProtocol_DS.pdf.

Google Scholar

[6]

PEH,LI-SHIUAN AND DALLY,WILLIAM J., "A Delay Model and Speculative Architecture for Pipelined Routers." Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan. 2001, pp. 255-266.

Digital Library

Google Scholar

[7]

SEITZ,CHARLES, "Let's Route Packets Instead of Wires." Advanced Research in VLSI: Proceedings of the Sixth MIT Conference, 1990, pp. 133-138.

Digital Library

Google Scholar

[8]

VSI Alliance, http://www.vsi.org.

Google Scholar

Cited By

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Kruszewski M(2024)How Shifting Focus from Register to Data Functionality Can Enhance Register and Bus ManagementElectronics10.3390/electronics1304071913:4(719)Online publication date: 9-Feb-2024
https://doi.org/10.3390/electronics13040719
Yuan JZhang JQiu PWei XLiu D(2024)A Survey of of Side-Channel Attacks and Mitigation for Processor InterconnectsApplied Sciences10.3390/app1415669914:15(6699)Online publication date: 31-Jul-2024
https://doi.org/10.3390/app14156699
Jonatan GCho HSon HWu XLivesay NMora EShivdikar KAbellán JJoshi AKaeli DKim J(2024)Scalability Limitations of Processing-in-Memory using Real System EvaluationsProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/36390468:1(1-28)Online publication date: 21-Feb-2024
https://dl.acm.org/doi/10.1145/3639046
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Route packets, not wires: on-chip inteconnection networks

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Published In

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 June 2001

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DAC01: 38th ACM/IEEE-CAS/ EDAC Design Automation Conference

Nevada, Las Vegas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Kruszewski M(2024)How Shifting Focus from Register to Data Functionality Can Enhance Register and Bus ManagementElectronics10.3390/electronics1304071913:4(719)Online publication date: 9-Feb-2024
https://doi.org/10.3390/electronics13040719
Yuan JZhang JQiu PWei XLiu D(2024)A Survey of of Side-Channel Attacks and Mitigation for Processor InterconnectsApplied Sciences10.3390/app1415669914:15(6699)Online publication date: 31-Jul-2024
https://doi.org/10.3390/app14156699
Jonatan GCho HSon HWu XLivesay NMora EShivdikar KAbellán JJoshi AKaeli DKim J(2024)Scalability Limitations of Processing-in-Memory using Real System EvaluationsProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/36390468:1(1-28)Online publication date: 21-Feb-2024
https://dl.acm.org/doi/10.1145/3639046
Ravikumar C(2024)Chiplets for Integration of Electronic SystemsIETE Journal of Education10.1080/09747338.2024.2311372(1-17)Online publication date: 15-Feb-2024
https://doi.org/10.1080/09747338.2024.2311372
Ouyang YZhang TLi JLiang H(2024)Fault-tolerant routing for reliable packet transmission in on-chip networksMicroelectronics Journal10.1016/j.mejo.2024.106425153(106425)Online publication date: Nov-2024
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Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-1Online publication date: 11-Jul-2024
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Weng XLiu YXu CLin XZhan LWang SChen DYang Y(2023)A Machine Learning Mapping Algorithm for NoC OptimizationSymmetry10.3390/sym1503059315:3(593)Online publication date: 25-Feb-2023
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Mountford TDhavlle ATevebaugh AMansoor NDinakarrao SGanguly A(2023)Address Obfuscation to Protect against Hardware Trojans in Network-on-ChipsJournal of Low Power Electronics and Applications10.3390/jlpea1303005013:3(50)Online publication date: 6-Sep-2023
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Reza M(2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
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Lyles DGonzalez-Guerrero PBautista MMichelogiannakis G(2023)PaST-NoC: A Packet-Switched Superconducting Temporal NoCIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.323624833:5(1-13)Online publication date: Aug-2023
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