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ICCAD 2006: San Jose, California, USA
- Soha Hassoun:
2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006. ACM 2006, ISBN 1-59593-389-1
Parasitic simulation and modeling
- Hong Li, Venkataramanan Balakrishnan
, Cheng-Kok Koh:
Stable and compact inductance modeling of 3-D interconnect structures. 1-6 - Hao Yu, Yiyu Shi, Lei He, David Smart
A fast block structure preserving model order reduction for inverse inductance circuits. 7-12 - Salvador Ortiz, Roberto Suaya:
Fullwave volumetric Maxwell solver using conduction modes. 13-18
Post-placement optimization techniques
- Murari Mani, Ashish Kumar Singh, Michael Orshansky:
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. 19-26 - Vaibhav Nawale, Thomas W. Chen:
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations. 27-32 - Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
State re-encoding for peak current minimization. 33-38
Variation modeling
- Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw:
A statistical framework for post-silicon tuning through body bias clustering. 39-46 - Kenichi Shinkai, Masanori Hashimoto
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. 47-53 - Xiaoji Ye, Peng Li, Frank Liu:
Practical variation-aware interconnect delay and slew analysis for statistical timing verification. 54-59 - Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao:
Analysis and modeling of CD variation for statistical static timing. 60-66
Embedded tutorial: from dual to multi to many core - opportunities and challenges for supporting the new exponential
- Jeff Parkhurst, John A. Darringer, Bill Grundmann:
From single core to multi-core: preparing for a new exponential. 67-72
Embedded tutorial: UML and SystemC for industrial ESL design - basic principles and applications
- Wolfgang Mueller, Alberto Rosti, Sara Bocchio, Elvinia Riccobene
UML for ESL design: basic principles, tools, and applications. 73-80
Efficient delay test generation
- Leonard Lee, Li-C. Wang
On bounding the delay of a critical path. 81-88 - Irith Pomeranz, Sudhakar M. Reddy:
A delay fault model for at-speed fault simulation and test generation. 89-95 - Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang:
Efficient Boolean characteristic function for fast timed ATPG. 96-99 - Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou:
Exploring linear structures of critical path delay faults to reduce test efforts. 100-106
Power grid analysis and design
- Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Fast decap allocation based on algebraic multigrid. 107-111 - Nestoras E. Evmorfopoulos, Dimitris P. Karampatzakis
Precise identification of the worst-case voltage drop conditions in power grid verification. 112-118 - Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail:
Importance of volume discretization of single and coupled interconnects. 119-126 - Nahi H. Abdul Ghani, Farid N. Najm:
Handling inductance in early power grid verification. 127-134
Optimization techniques for different target technologies
- Gordon R. Chiu, Deshanand P. Singh
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. 135-142 - Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton:
Factor cuts. 143-150 - Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m). 151-157 - Yu Zhou, Danil Sokolov, Alexandre Yakovlev
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. 158-163
Placement and floorplanning
- Chuan Lin, Hai Zhou, Chris C. N. Chu:
A revisit to floorplan optimization by Lagrangian relaxation. 164-171 - Tan Yan, Hiroshi Murata:
Fast wire length estimation by net bundling for block placement. 172-178 - Peter Spindler, Frank M. Johannes:
Fast and robust quadratic placement combined with an exact linear net model. 179-186 - Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. 187-192
Digital and RF test and reliability
- Feng Shi, Yiorgos Makris
Testing delay faults in asynchronous handshake circuits. 193-197 - Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
A novel framework for faster-than-at-speed delay test considering IR-drop effects. 198-203 - Mihir R. Choudhury, Quming Zhou, Kartik Mohanram:
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. 204-209 - Erkan Acar, Sule Ozev, Kevin B. Redmond:
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers. 210-216
Statistical timing analysis
- Sari Onaissi, Farid N. Najm:
A linear-time approach for static timing analysis covering all process corners. 217-224 - Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
A framework for statistical timing analysis using non-linear delay and slew models. 225-230 - Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis. 231-236 - Kaviraj Chopra, Bo Zhai, David T. Blaauw, Dennis Sylvester:
A new statistical max operation for propagating skewness in statistical timing analysis. 237-243
Power and performance optimizations on system level design
- Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy:
Cache miss clustering for banked memory systems. 244-250 - Seok-Won Seong, Prabhat Mishra
A bitmask-based code compression technique for embedded systems. 251-254 - Jian-Jia Chen
Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems. 255-260 - David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
Application-specific customization of parameterized FPGA soft-core processors. 261-268
Analog simulation and verification
- Xiaolue Lai, Jaijeet S. Roychowdhury:
TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. 269-274 - Scott Little, Nicholas Seegmiller, David Walter
Verification of analog/mixed-signal circuits using labeled hybrid petri nets. 275-282 - Ting Mei, Jaijeet S. Roychowdhury:
PPV-HB: harmonic balance for oscillator/PLL phase macromodels. 283-288
Self adaptation and physical awareness in high-level synthesis
- Gennette Gill, John Hansen, Montek Singh:
Loop pipelining for high-throughput stream computation using self-timed rings. 289-296 - Min Ni, Seda Ogrenci Memik:
Thermal-induced leakage power optimization by redundant resource allocation. 297-302 - Wei-Lun Hung, Xiaoxia Wu, Yuan Xie:
Guaranteeing performance yield in high-level synthesis. 303-309
Advances in performance modeling for interconnect and memory
- Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra:
Information theoretic approach to address delay and reliability in long on-chip interconnects. 310-314 - Bin Zhang, Ari Arapostathis
Analytical modeling of SRAM dynamic stability. 315-322 - Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner:
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. 323-328
Embedded tutorial: design and CAD challenges in 45nm CMOS and beyond - from front to back
- David J. Frank, Ruchir Puri, Dorel Toma:
Design and CAD challenges in 45nm CMOS and beyond. 329-333
Analog design automation techniques
- Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli:
Robust system level design with analog platforms. 334-341 - Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi:
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. 342-348 - Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu:
Analog placement with symmetry and other placement constraints. 349-354
Challenges on system level interconnection
- Srinivasan Murali, Paolo Meloni
Designing application-specific networks on chips with floorplan information. 355-362 - Gunar Schirner
Fast and accurate transaction level models using result oriented modeling. 363-368 - Yeow Meng Chee
Optimal memoryless encoding for low power off-chip data buses. 369-374
Placement optimization: timing, noise, and power
- Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar:
A network-flow approach to timing-driven incremental placement for ASICs. 375-382 - Bo Hu:
Timing-driven placement for heterogeneous field programmable gate array. 383-388 - Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
Voltage island aware floorplanning for power and timing optimization. 389-394 - Eric Wong, Jacob R. Minz, Sung Kyu Lim
Decoupling capacitor planning and sizing for noise and leakage reduction. 395-400
Timing and power analysis
- Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou:
A timing dependent power estimation framework considering coupling. 401-407 - Kenneth S. Stevens, Florentin Dartu:
Algorithms for MIS vector generation and pruning. 408-414 - Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng:
Timing model reduction for hierarchical timing analysis. 415-422 - Sean X. Shi, Peng Yu, David Z. Pan:
A unified non-rectangular device and circuit simulation model for timing and power. 423-428
Thermal and variability issues in architectures
- Xiaoyao Liang, David M. Brooks:
Microarchitecture parameter selection to optimize system performance under process variation. 429-436 - Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik:
Thermal sensor allocation and placement for reconfigurable systems. 437-442 - Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan:
Thermal characterization and optimization in platform FPGAs. 443-447 - Jorge Júlvez, Jordi Cortadella
Performance analysis of concurrent systems with early evaluation. 448-455
Embedded tutorial: automation in mixed-signal design - reality check and the nano challenge
- Christopher Labrecque:
Near-term industrial perspective of analog CAD. 456-457 - Rob A. Rutenbar
Design automation for analog: the next generation of tool challenges. 458-460 - Trent McConaghy, Georges G. E. Gielen:
Automation in mixed-signal design: challenges and solutions in the wake of the nano era. 461-463
Global routing
- Min Pan, Chris C. N. Chu:
FastRoute: a step to integrate global routing into placement. 464-471 - Devang Jariwala, John Lillis:
Trunk decomposition based global routing optimization. 472-479 - Dirk Müller:
Optimizing yield in global routing. 480-486 - Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri:
Wire density driven global routing for CMP variation and timing. 487-492
Emerging topics in signal integrity and reliability
- Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
An analytical model for negative bias temperature instability. 493-496 - Hossein Asadi
Soft error derating computation in sequential circuits. 497-501 - Rajeev R. Rao, David T. Blaauw, Dennis Sylvester:
Soft error reduction in combinational logic using gate resizing and flipflop selection. 502-509 - Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu
Current path analysis for electrostatic discharge protection. 510-515
Fault-tolerant energy minimization techniques for real-time embedded systems
- Xiliang Zhong, Cheng-Zhong Xu
System-wide energy minimization for real-time tasks: lower bound and approximation. 516-521 - Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang:
Online task-scheduling for fault-tolerant low-energy real-time systems. 522-527 - Dakai Zhu, Hakan Aydin:
Energy management for real-time embedded systems with reliability requirements. 528-534
Emerging issues in contemporaneous system level design
- Shuo Wang, Lei Wang:
Exploiting soft redundancy for error-resilient on-chip memory design. 535-540 - Diana Marculescu
System-level process-driven variability analysis for single and multiple voltage-frequency island systems. 541-546 - Rajarshi Mukherjee, Seda Ogrenci Memik:
Physical aware frequency selection for dynamic thermal management in multi-core systems. 547-552
Clock and buffer synthesis
- Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi:
A new RLC buffer insertion algorithm. 553-557 - Rupak Samanta, Ganesh Venkataraman, Jiang Hu:
Clock buffer polarity assignment for power noise reduction. 558-562 - Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li:
Combinatorial algorithms for fast clock mesh optimization. 563-567
Thermal analysis for the nano scale
- Sheng-Chih Lin, Kaustav Banerjee:
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. 568-574 - Yonghong Yang, Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick:
Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design. 575-582 - Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy:
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. 583-586
Advances in embedded system design
- Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Runtime distribution-aware dynamic voltage scaling. 587-594 - Ilie I. Luican, Hongwei Zhu, Florin Balasa:
Formal model of data reuse analysis for hierarchical memory organizations. 595-600 - Chin-Hsien Wu, Tei-Wei Kuo
An adaptive two-level management for the flash translation layer in embedded systems. 601-606
Architectural design techniques for high performance and robustness
- Raj Varada, Mysore Sriram, Kris Chou, James Guzzo:
Design and integration methods for a multi-threaded dual core 65nm Xeon® processor. 607-610 - Manoj Ampalam, Montek Singh:
Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. 611-618 - Swaroop Ghosh, Swarup Bhunia
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. 619-624
Manufacturability and power in layout
- Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai:
Efficient process-hotspot detection using range pattern matching. 625-632 - Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration. 633-640 - Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu:
Post-placement voltage island generation. 641-646
Embedded tutorial: emerging nanoelectronics - prospects, state of the art and opportunities for CAD
- Jeffrey Bokor:
Prospects for emerging nanoelectronics in mainstream information processing systems. 647-648 - Jia Chen:
Carbon nanotubes for potential electronic and optoelectronic applications. 649-650 - H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan:
Carbon nanotube transistor circuits: models and tools for design and performance optimization. 651-654
Technology driven layout methodologies
- Xiaoping Tang, Xin Yuan:
Technology migration techniques for simplified layouts with restrictive design rules. 655-660 - Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky
Fill for shallow trench isolation CMP. 661-668 - Zhe-Wei Jiang, Yao-Wen Chang
An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. 669-674
Novel FPGA architectures, techniques and designs
- Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. 675-679 - Marvin Tom, David Leong, Guy G. Lemieux:
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. 680-687 - Xin Jia, Ranga Vemuri
Studying a GALS FPGA architecture using a parameterized automatic design flow. 688-693 - David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen
Conjoining soft-core FPGA processors. 694-701
Specification and architecture challenges in high-level synthesis
- Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor. 702-708 - Jason Cong, Yiping Fan, Wei Jiang:
Platform-based resource binding using a distributed register-file microarchitecture. 709-715 - Greg Stitt, Frank Vahid, Walid A. Najjar
A code refinement methodology for performance-improved synthesis from C. 716-723 - Girish Venkataramani, Seth Copen Goldstein:
Leveraging protocol knowledge in slack matching. 724-729
Defect tolerance for nanoscale architectures
- Mehdi Baradaran Tahoori:
Application-independent defect-tolerant crossbar nano-architectures. 730-734 - Eric Rachlin, John E. Savage:
Nanowire addressing with randomized-contact decoders. 735-742 - Gang Wang, Wenrui Gong, Ryan Kastner
On the use of Bloom filters for defect maps in nanocomputing. 743-746
Dynamic power management
- Gaurav Dhiman, Tajana Simunic Rosing:
Dynamic power management using machine learning. 747-754 - Mehrdad Najibi, Mostafa E. Salehi
Dynamic voltage and frequency management based on variable update intervals for frequency setting. 755-760 - Lin Yuan, Sean Leventhal, Gang Qu:
Temperature-aware leakage minimization technique for real-time systems. 761-764 - Daler N. Rakhmatov:
Energy budgeting for battery-powered sensors with a known task schedule. 765-771
Advances in model checking
- Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer
Stepping forward with interpolants in unbounded model checking. 772-778 - David Ward, Fabio Somenzi:
Decomposing image computation for symbolic reachability analysis using control flow information. 779-785 - Panagiotis Manolios
Automatic memory reductions for RTL model verification. 786-793 - Malay K. Ganai, Aarti Gupta
Accelerating high-level bounded model checking. 794-801
Novel interconnect methodologies
- Hao Yu, Joanna Ho, Lei He:
Simultaneous power and thermal integrity driven via stapling in 3D ICs. 802-808 - Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli
Yield prediction for 3D capacitive interconnections. 809-814 - Renshen Wang, Rui Shi, Chung-Kuan Cheng:
Layer minimization of escape routing in area array packaging. 815-819 - Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
Network coding for routability improvement in VLSI. 820-823
Embedded tutorial: integrating nanoelectronics, biotechnology and MEMS/NEMS
- Bernhard E. Boser:
From micro to nano: MEMS as an interface to the nano world. 824-825 - Ann Witvrouw
CMOS-MEMS integration: why, how and what? 826-827 - Richard A. Kiehl:
Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures. 828-829 - Vladimir Bulovic, Kyungbum Kevin Ryu, Charles G. Sodini, Ioannis Kymissis, Annie Wang, Ivan Nausieda, Akintunde Ibitayo Akinwande:
Molecular organic electronic circuits. 830-831 - Conor F. Madigan, Vladimir Bulovic:
Organic electronic device modeling at the nanoscale. 832-833
Embedded tutorial: variability and yield improvement: rules, models, and characterization
- Kenneth L. Shepard, Daniel N. Maynard:
Variability and yield improvement: rules, models, and characterization. 834-835
Accelerating verification
- Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén:
Improvements to combinational equivalence checking. 836-843 - Hossein M. Sheini, Karem A. Sakallah:
SMT(CLU): a step toward scalability in system verification. 844-851 - Zhaohui Fu, Sharad Malik
Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. 852-859 - Beth Isaksen, Valeria Bertacco:
Verification through the principle of least astonishment. 860-867
Model order reduction and parametric analysis
- Zhuo Feng, Peng Li:
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. 868-875 - Saurabh K. Tiwary, Rob A. Rutenbar:
Faster, parametric trajectory-based macromodels via localized linear reductions. 876-883 - Wei-Shen Wang, Michael Orshansky:
Robust estimation of parametric yield under limited descriptions of uncertainty. 884-890
Design and modeling of molecular-scale systems
- Josep Carmona
From molecular interactions to gates: a systematic approach. 891-898 - Shih-Hsien Kuo, Jacob White:
A spectrally accurate integral equation solver for molecular surface electrostatics. 899-906 - Michael T. Niemier, Michael Crocker, Xiaobo Sharon Hu
Using CAD to shape experiments in molecular QCA. 907-914
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