Article

Platform-based resource binding using a distributed register-file microarchitecture

Authors:

Wei JiangAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 709 - 715

https://doi.org/10.1145/1233501.1233648

Published: 05 November 2006 Publication History

Abstract

Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

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Cited By

Cong JLiu BGroeneveld PSciuto DHassoun S(2012)A metric for layout-friendly microarchitecture optimization in high-level synthesisProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228587(1239-1244)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228587
Cong JLiu BLuo GPrabhakar RHu JKoh C(2012)Towards layout-friendly high-level synthesisProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160952(165-172)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160952
Cong JLiu BXu JDe Micheli GAl-Hashimi BMueller WMacii E(2010)Coordinated resource optimization in behavioral synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871230(1267-1272)Online publication date: 8-Mar-2010
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Index Terms

Platform-based resource binding using a distributed register-file microarchitecture
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

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Cited By

Cong JLiu BGroeneveld PSciuto DHassoun S(2012)A metric for layout-friendly microarchitecture optimization in high-level synthesisProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228587(1239-1244)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228587
Cong JLiu BLuo GPrabhakar RHu JKoh C(2012)Towards layout-friendly high-level synthesisProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160952(165-172)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160952
Cong JLiu BXu JDe Micheli GAl-Hashimi BMueller WMacii E(2010)Coordinated resource optimization in behavioral synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871230(1267-1272)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871230
Cong JHuang HJiang WDe Micheli GAl-Hashimi BMueller WMacii E(2010)A generalized control-flow-aware pattern recognition algorithm for behavioral synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871228(1255-1260)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871228
Cong JLiu BMajumdar RZhang Z(2010)Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011316:1(1-29)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1145/1870109.1870113
Chen CHuang JWakabayashi K(2009)CriASProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509651(67-72)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509651
Cong JLiu BZhang ZRoychowdhury J(2009)Scheduling with soft constraintsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687410(47-54)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687410
Cong JFan YXu J(2009)Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitectureACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1529255.152925714:3(1-31)Online publication date: 4-Jun-2009
https://dl.acm.org/doi/10.1145/1529255.1529257
Casseau ELe Gal B(2009)High-level synthesis for the design of FPGA-based signal processing systems2009 International Symposium on Systems, Architectures, Modeling, and Simulation10.1109/ICSAMOS.2009.5289238(25-32)Online publication date: Jul-2009
https://doi.org/10.1109/ICSAMOS.2009.5289238
Chia-I Chen Huang J(2009)CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796443(67-72)Online publication date: Jan-2009
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