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Somsubhra Mondal
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2000 – 2009
- 2008
- [j2]Seda Ogrenci Memik, Nikolaos Bellas
, Somsubhra Mondal:
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2027-2038 (2008) - [j1]Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal:
A high-level clustering algorithm targeting dual Vdd FPGAs. ACM Trans. Design Autom. Electr. Syst. 13(4): 57:1-57:20 (2008) - 2006
- [c10]Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik:
A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. ERSA 2006: 56-62 - [c9]Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. FCCM 2006: 325-326 - [c8]Somsubhra Mondal, Seda Ogrenci Memik:
Power Optimization Techniques for SRAM-Based FPGAs. FPL 2006: 1-2 - [c7]Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. FPL 2006: 1-4 - [c6]Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik:
Thermal sensor allocation and placement for reconfigurable systems. ICCAD 2006: 437-442 - [c5]Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik:
Fine-grain thermal profiling and sensor insertion for FPGAs. ISCAS 2006 - 2005
- [c4]Somsubhra Mondal, Seda Ogrenci Memik:
Resource sharing in pipelined CDFG synthesis. ASP-DAC 2005: 795-798 - [c3]Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das:
Hierarchical LUT structures for leakage power reduction (abstract only). FPGA 2005: 272 - [c2]Somsubhra Mondal, Seda Ogrenci Memik:
Fine-grain leakage optimization in SRAM based FPGAs. ACM Great Lakes Symposium on VLSI 2005: 238-243 - [c1]Somsubhra Mondal, Seda Ogrenci Memik:
A low power FPGA routing architecture. ISCAS (2) 2005: 1222-1225
Coauthor Index
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