default search action
Michael Kishinevsky
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
- [j38]Shruti Yadav Narayana
, Sumit K. Mandal
Fast Analysis Using Finite Queuing Model for Multilayer NoCs. IEEE Des. Test 40(6): 112-124 (2023) - [j37]Ümit Y. Ogras
Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques. ACM Trans. Embed. Comput. Syst. 22(2): 27:1-27:3 (2023) - [j36]Anish Krishnakumar
Domain-Specific Architectures: Research Problems and Promising Approaches. ACM Trans. Embed. Comput. Syst. 22(2): 28:1-28:26 (2023) - [j35]Gaurav Narang
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework. ACM Trans. Design Autom. Electr. Syst. 28(5): 84:1-84:21 (2023) - [j34]Sumit K. Mandal
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 670-683 (2023) - [c87]Shruti Yadav Narayana, Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras:
A Lightweight Congestion Control Technique for NoCs with Deflection Routing. DATE 2023: 1-2 - [c86]Gaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande:
Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems. ISLPED 2023: 1-6 - [i9]Shruti Yadav Narayana, Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras
Machine Learning-based Low Overhead Congestion Control Algorithm for Industrial NoCs. CoRR abs/2302.12779 (2023) - [i8]Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Machine Learning for Microprocessor Performance Bug Localization. CoRR abs/2303.15280 (2023) - 2022
- [c85]Jaroslaw Sydir, Bin Li, Pietro Mercati, Charlie Tai, Ravi R. Iyer, Michael Kishinevsky, Boris Serafimov:
DPM-NFV: Dynamic Power Management Framework for 5G User Plane Function using Bayesian Optimization. GLOBECOM 2022: 4099-4105 - 2021
- [j33]Qian Li
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization. IEEE Comput. Archit. Lett. 20(1): 46-49 (2021) - [j32]Sumit K. Mandal
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic. IEEE Embed. Syst. Lett. 13(3): 98-101 (2021) - [c84]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz
Automatic Microprocessor Performance Bug Detection. HPCA 2021: 545-556 - [c83]Sumit K. Mandal, Jie Tong, Raid Ayoub, Michael Kishinevsky, Ahmed Abousamra, Ümit Y. Ogras
Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration. ICCAD 2021: 1-9 - [c82]Pietro Mercati, Bin Li, Mesut Ali Ergin, Charlie Tai, Michael Kishinevsky, Boris Serafimov, Subhiksha Ravisundar, Eoin Walsh, Thomas Long:
MOBO-NFV: Automated Tuning of a Network Function Virtualization System using Multi-Objective Bayesian Optimization. IM 2021: 90-98 - [i7]Sumit K. Mandal, Jie Tong, Raid Ayoub, Michael Kishinevsky, Ahmed Abousamra, Ümit Y. Ogras:
Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration. CoRR abs/2108.09534 (2021) - 2020
- [j31]Ümit Y. Ogras
Guest Editors' Introduction: Design and Management of Mobile Platforms: From Smartphones to Wearable Devices. IEEE Des. Test 37(5): 5-6 (2020) - [j30]Sudeep Pasricha
A Survey on Energy Management for Mobile and IoT Devices. IEEE Des. Test 37(5): 7-24 (2020) - [c81]Sumit K. Mandal, Ümit Y. Ogras
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs. DAC 2020: 1-6 - [c80]Sumit K. Mandal, Anish Krishnakumar, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras
Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion. ICCAD 2020: 42:1-42:9 - [c79]Raid Ayoub, Michael Kishinevsky, Sumit K. Mandal, Ümit Y. Ogras:
Analytical modeling of NoCs for fast simulation and design exploration (invited). SLIP 2020: 8 - [i6]Ujjwal Gupta, Manoj Babu, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Suat Gumussoy, Ümit Y. Ogras:
An Online Learning Methodology for Performance Modeling of Graphics Processors. CoRR abs/2003.11740 (2020) - [i5]Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Mohammad M. Islam, Ümit Y. Ogras:
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic. CoRR abs/2007.13951 (2020) - [i4]Sumit K. Mandal, Anish Krishnakumar, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras:
Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion. CoRR abs/2008.03904 (2020) - [i3]Sumit K. Mandal, Ümit Y. Ogras, Janardhan Rao Doppa, Raid Zuhair Ayoub, Michael Kishinevsky, Partha Pratim Pande:
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs. CoRR abs/2008.09728 (2020) - [i2]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. CoRR abs/2011.08781 (2020)
2010 – 2019
- 2019
- [j29]Kenneth O'Neal
Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1133-1146 (2019) - [j28]Sumit K. Mandal
Analytical Performance Models for NoCs with Multiple Priority Traffic Classes. ACM Trans. Embed. Comput. Syst. 18(5s): 52:1-52:21 (2019) - [c78]David Ke Hong, Ashkan Nikravesh, Z. Morley Mao, Mahesh Ketkar, Michael Kishinevsky:
PerfProbe: a systematic, cross-layer performance diagnosis framework for mobile platforms. MOBILESoft@ICSE 2019: 50-61 - [c77]Emirhan Poyraz, Prethvi Kashinkunti, Matthew Schuchhardt, Michael Kishinevsky, Niranjan Soundararajan, Gokhan Memik:
Understanding the impact of number of CPU cores on user satisfaction in smartphones. MobiQuitous 2019: 288-297 - [i1]Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras:
Analytical Performance Models for NoCs with Multiple Priority Traffic Classes. CoRR abs/1908.02408 (2019) - 2018
- [j27]Ujjwal Gupta
An Online Learning Methodology for Performance Modeling of Graphics Processors. IEEE Trans. Computers 67(12): 1677-1691 (2018) - [j26]Ujjwal Gupta
Dynamic Power Budgeting for Mobile Systems Running Graphics Workloads. IEEE Trans. Multi Scale Comput. Syst. 4(1): 30-40 (2018) - [c76]Ujjwal Gupta, Manoj Babu, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Ümit Y. Ogras
STAFF: online learning with stabilized adaptive forgetting factor and feature selection algorithm. DAC 2018: 177:1-177:6 - 2017
- [j25]Begum Egilmez, Matthew Schuchhardt, Gokhan Memik, Raid Ayoub, Niranjan Soundararajan, Michael Kishinevsky:
User-aware Frame Rate Management in Android Smartphones. ACM Trans. Embed. Comput. Syst. 16(5s): 131:1-131:17 (2017) - [c75]Francesco Paterna, Ujjwal Gupta, Raid Ayoub, Ümit Y. Ogras
Adaptive Performance Sensitivity Model to Support GPU Power Management. ANDARE@PACT 2017: 5:1-5:6 - [c74]Pietro Mercati
Multi-variable Dynamic Power Management for the GPU Subsystem. DAC 2017: 2:1-2:6 - [c73]Kenneth O'Neal, Philip Brisk
HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. DAC 2017: 80:1-80:6 - 2016
- [c72]Ujjwal Gupta, Joseph Campbell, Ümit Y. Ogras
Adaptive performance prediction for integrated GPUs. ICCAD 2016: 61 - 2015
- [j24]Jordi Cortadella
RTL Synthesis: From Logic Synthesis to Automatic Pipelining. Proc. IEEE 103(11): 2061-2075 (2015) - [c71]Matthew Schuchhardt, Susmit Jha, Raid Ayoub, Michael Kishinevsky, Gokhan Memik:
Optimizing mobile display brightness by leveraging human visual perception. CASES 2015: 11-20 - [c70]David Kadjo, Raid Ayoub, Michael Kishinevsky, Paul V. Gratz
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms. DAC 2015: 62:1-62:6 - [c69]Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Ümit Y. Ogras
Multi-product floorplan and uncore design framework for chip multiprocessors. SLIP 2015: 1-7 - 2014
- [c68]Matthew Schuchhardt, Susmit Jha, Raid Ayoub, Michael Kishinevsky, Gokhan Memik:
CAPED: Context-aware personalized display brightness for mobile devices. CASES 2014: 19:1-19:10 - [c67]David Kadjo, Ümit Y. Ogras
Towards platform level power management in mobile systems. SoCC 2014: 146-151 - 2013
- [j23]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Trans. Design Autom. Electr. Syst. 18(4): 47:1-47:21 (2013) - [c66]Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. DAC 2013: 114:1-114:7 - [c65]Ümit Y. Ogras
Managing mobile platform power. ICCAD 2013: 161-162 - 2012
- [j22]Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras
xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification. IEEE Des. Test Comput. 29(3): 80-88 (2012) - [j21]Satrajit Chatterjee, Michael Kishinevsky:
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics. Formal Methods Syst. Des. 40(2): 147-169 (2012) - [c64]Daniel E. Holcomb, Alexander Gotmanov, Michael Kishinevsky, Sanjit A. Seshia:
Compositional performance verification of NoC designs. MEMOCODE 2012: 1-10 - [c63]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. NOCS 2012: 43-50 - [c62]Ümit Y. Ogras, Michael Kishinevsky:
Design and optimization of communication fabrics: an industrial perspective. SLIP 2012: 19 - [c61]Ümit Y. Ogras
Energy-guided exploration of on-chip network design for exa-scale computing. SLIP 2012: 24-31 - 2011
- [j20]Josep Carmona
A Scheduling Strategy for Synchronous Elastic Designs. Fundam. Informaticae 108(1-2): 1-21 (2011) - [j19]Marc Galceran Oms, Alexander Gotmanov, Jordi Cortadella
Microarchitectural Transformations Using Elasticity. ACM J. Emerg. Technol. Comput. Syst. 7(4): 18:1-18:24 (2011) - [c60]Michael Kishinevsky, Alexander Gotmanov, Yuriy Viktorov:
Challenges in Verifying Communication Fabrics. ITP 2011: 18-21 - [c59]Chen-Ling Chou, Radu Marculescu
System interconnect design exploration for embedded MPSoCs. SLIP 2011: 1-8 - [c58]Alexander Gotmanov, Satrajit Chatterjee, Michael Kishinevsky:
Verifying Deadlock-Freedom of Communication Fabrics. VMCAI 2011: 214-231 - [e2]Satnam Singh, Barbara Jobstmann, Michael Kishinevsky, Jens Brandt:
9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011. IEEE 2011, ISBN 978-1-4577-0117-7 [contents] - [e1]Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha:
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011. ACM/IEEE Computer Society 2011, ISBN 978-1-4503-0720-8 [contents] - 2010
- [j18]Jorge Júlvez, Jordi Cortadella
On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics. Discret. Event Dyn. Syst. 20(3): 377-407 (2010) - [j17]Josep Carmona
New Region-Based Algorithms for Deriving Bounded Petri Nets. IEEE Trans. Computers 59(3): 371-384 (2010) - [c57]Satrajit Chatterjee, Michael Kishinevsky:
Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. CAV 2010: 321-338 - [c56]Marc Galceran Oms, Jordi Cortadella, Dmitry Bufistov, Michael Kishinevsky:
Automatic microarchitectural pipelining. DATE 2010: 961-964 - [c55]Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras
Quick formal modeling of communication fabrics to enable verification. HLDVT 2010: 42-49 - [c54]Marc Galceran Oms, Jordi Cortadella
Symbolic performance analysis of elastic systems. ICCAD 2010: 778-785 - [c53]Jordi Cortadella
Elastic systems. MEMOCODE 2010: 149-158 - [c52]Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. NOCS 2010: 125-134
2000 – 2009
- 2009
- [j16]David Bañeres
A Recursive Paradigm to Solve Boolean Relations. IEEE Trans. Computers 58(4): 512-527 (2009) - [j15]Josep Carmona
Elastic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1437-1455 (2009) - [c51]Josep Carmona
Scheduling Synchronous Elastic Designs. ACSD 2009: 52-59 - [c50]Josep Carmona
Genet: A Tool for the Synthesis and Mining of Petri Nets. ACSD 2009: 181-185 - [c49]Josep Carmona
Divide-and-Conquer Strategies for Process Mining. BPM 2009: 327-343 - [c48]Dmitry Bufistov, Jordi Cortadella
Retiming and recycling for elastic systems with early evaluation. DAC 2009: 288-291 - [c47]Marc Galceran Oms, Jordi Cortadella
Speculation in elastic systems. DAC 2009: 292-295 - [c46]David Bañeres
Variable-latency design by function speculation. DATE 2009: 1704-1709 - [c45]David Bañeres
Timing-driven N-way decomposition. ACM Great Lakes Symposium on VLSI 2009: 363-368 - 2008
- [j14]Jordi Cortadella
Elasticity and Petri Nets. Trans. Petri Nets Other Model. Concurr. 1: 221-249 (2008) - [c44]Michael Kishinevsky, Jordi Cortadella
Time elastic digital systems and Petri Nets. ACSD 2008: 1-2 - [c43]Josep Carmona
A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. Petri Nets 2008: 92-111 - [c42]Josep Carmona, Jordi Cortadella
A Region-Based Algorithm for Discovering Petri Nets from Event Logs. BPM 2008: 358-373 - [c41]Timothy Kam, Michael Kishinevsky, Jordi Cortadella
Correct-by-construction microarchitectural pipelining. ICCAD 2008: 434-441 - [c40]Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang:
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. MEMOCODE 2008: 79-88 - 2007
- [j13]Michael Kishinevsky, Sandeep K. Shukla
Guest Editors' Introduction: GALS Design and Validation. IEEE Des. Test Comput. 24(5): 414-416 (2007) - [c39]Jordi Cortadella
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. DAC 2007: 416-419 - [c38]David Bañeres, Jordi Cortadella, Michael Kishinevsky:
Layout-aware gate duplication and buffer insertion. DATE 2007: 1367-1372 - [c37]Dmitry Bufistov, Jordi Cortadella
A general model for performance optimization of sequential systems. ICCAD 2007: 362-369 - 2006
- [c36]Michael Kishinevsky, Jordi Cortadella
Synchronous Elastic Circuits. CSR 2006: 3-5 - [c35]Jordi Cortadella
Synthesis of synchronous elastic architectures. DAC 2006: 657-662 - [c34]Sava Krstic, Jordi Cortadella
Synchronous Elastic Networks. FMCAD 2006: 19-30 - [c33]David Bañeres, Jordi Cortadella
Dominator-based partitioning for delay optimization. ACM Great Lakes Symposium on VLSI 2006: 67-72 - [c32]Jorge Júlvez, Jordi Cortadella
Performance analysis of concurrent systems with early evaluation. ICCAD 2006: 448-455 - 2004
- [c31]David Bañeres
A recursive paradigm to solve Boolean relations. DAC 2004: 416-421 - [c30]Laurent Arditi, Gérard Berry, Michael Kishinevsky:
Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. FMCAD 2004: 128-143 - 2003
- [c29]Gérard Berry, Michael Kishinevsky, Satnam Singh:
System Level Design and Verification Using a Synchronous Language. ICCAD 2003: 433-440 - 2002
- [j12]Jordi Cortadella
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 109-130 (2002) - [c28]Sumit Gupta, Nick Savoiu, Nikil D. Dutt
Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903 - 2000
- [c27]Jordi Cortadella
Hardware and Petri Nets: Application to Asynchronous Circuit Design. ICATPN 2000: 1-15
1990 – 1999
- 1999
- [j11]Alex Kondratyev, Jordi Cortadella
Logic decomposition of speed-independent circuits. Proc. IEEE 87(2): 347-362 (1999) - [j10]Jordi Cortadella
Decomposition and technology mapping of speed-independent circuits using Boolean relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1221-1236 (1999) - [c26]Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. DAC 1999: 110-115 - [c25]Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella
CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121 - [c24]Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens:
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD 1999: 324-331 - 1998
- [j9]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten:
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings. Formal Methods Syst. Des. 12(1): 5-38 (1998) - [j8]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Jordi Cortadella
The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. J. Circuits Syst. Comput. 8(1): 67-118 (1998) - [j7]Jordi Cortadella
Deriving Petri Nets for Finite Transition Systems. IEEE Trans. Computers 47(8): 859-882 (1998) - [j6]Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
Hazard-free implementation of speed-independent circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 749-771 (1998) - [j5]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin:
Partial-scan delay fault testing of asynchronous circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1184-1199 (1998) - [c23]Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev:
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. ACSD 1998: 152-163 - [c22]Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev:
Asynchronous Interface Specification, Analysis and Synthesis. DAC 1998: 2-7 - [c21]Jordi Cortadella
Lazy transition systems: application to timing optimization of asynchronous circuits. ICCAD 1998: 324-331 - 1997
- [j4]Jordi Cortadella
A region-based theory for state assignment in speed-independent circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 793-812 (1997) - [c20]Michael Kishinevsky, Jordi Cortadella
Coupling Asynchrony and Interrupts: Place Chart Nets. ICATPN 1997: 328-347 - [c19]Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev:
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. ASYNC 1997: 240-253 - [c18]Jordi Cortadella
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. ED&TC 1997: 98-105 - [c17]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev:
Decomposition and technology mapping of speed-independent circuits using Boolean relations. ICCAD 1997: 220-227 - [c16]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin:
Partial scan delay fault testing of asynchronous circuits. ICCAD 1997: 728-735 - 1996
- [j3]Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny:
On the Models for Asynchronous Circuit Behaviour with OR Causality. Formal Methods Syst. Des. 9(3): 189-233 (1996) - [c15]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten:
A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings. Application and Theory of Petri Nets 1996: 346-365 - [c14]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Yakovlev:
Complete state encoding based on the theory of regions. ASYNC 1996: 36-47 - [c13]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev:
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. DAC 1996: 63-66 - 1995
- [c12]Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev:
On hazard-free implementation of speed-independent circuits. ASP-DAC 1995 - [c11]Alex Kondratyev, Jordi Cortadella
Checking signal transition graph implementability by symbolic BDD traversal. ED&TC 1995: 325-332 - [c10]Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
Synthesizing Petri nets from state-based models. ICCAD 1995: 164-171 - 1994
- [j2]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky:
Analysis and Identification of Speed-Independent Circuits on an Event Model. Formal Methods Syst. Des. 4(1): 33-75 (1994) - [j1]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin:
Specification and analysis of self-timed circuits. J. VLSI Signal Process. 7(1-2): 117-135 (1994) - [c9]Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno:
OR Causality: Modelling and Hardware Implementation. Application and Theory of Petri Nets 1994: 568-587 - [c8]Michael Kishinevsky, Jørgen Staunstrup:
Characterizing speed-independence of high-level designs. ASYNC 1994: 44-53 - [c7]Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev:
Basic Gate Implementation of Speed-Independent Circuits. DAC 1994: 56-62 - [c6]Christian D. Nielsen
Performance Analysis Based on Timing Simulation. DAC 1994: 70-76 - [c5]Luciano Lavagno, Antonio Lioy, Michael Kishinevsky:
Testing redundant asynchronous circuits by variable phase splitting. EURO-DAC 1994: 328-333 - [c4]Alex Kondratyev, Alexander Taubin, Victor Varshavsky, Michael Kishinevsky, Edwige E. Pissaloux:
Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems. PDP 1994: 220-226 - [c3]Michael Kishinevsky, Jørgen Staunstrup:
Mechanized Verification of Speed-independence. TPCD 1994: 146-164 - 1992
- [c2]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky:
Analysis and Identification of Self-Timed Circuits. Designing Correct Circuits 1992: 275-287 - 1991
- [c1]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin:
Formal method for self-timed design. EURO-DAC 1991: 197-201
Coauthor Index
Raid Ayoub
aka: Raid Zuhair Ayoub
aka: Raid Zuhair Ayoub
[j24] [j20] [j19] [j18] [j17] [c56] [c54] [c53] [c52] [j16] [j15] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [j14] [c44] [c43] [c42] [c41] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j12] [c27] [j11] [j10] [c26] [c25] [c24] [j8] [j7] [c23] [c22] [c21] [j4] [c20] [c19] [c18] [c17] [c14] [c13] [c11] [c10]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: