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Sarvesh H. Kulkarni
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2010 – 2019
- 2017
- [j7]Zhanping Chen
, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya:
A 0.9-μm2 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming. IEEE J. Solid State Circuits 52(4): 933-939 (2017) - 2016
- [j6]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 51(4): 1003-1008 (2016) - [c8]Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. VLSI Circuits 2016: 1-2 - 2015
- [c7]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process. VLSIC 2015: 174- - 2010
- [j5]Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang:
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. IEEE J. Solid State Circuits 45(4): 863-868 (2010)
2000 – 2009
- 2008
- [j4]Yih Wang
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43(1): 172-179 (2008) - [j3]Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw:
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 481-494 (2008) - 2007
- [c6]Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr:
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. ISSCC 2007: 324-606 - 2006
- [j2]Sarvesh H. Kulkarni, Dennis Sylvester:
Power Distribution Techniques for Dual VDD Circuits. J. Low Power Electron. 2(2): 217-229 (2006) - [c5]Sarvesh H. Kulkarni, Dennis Sylvester:
Power distribution techniques for dual VDD circuits. ASP-DAC 2006: 838-843 - [c4]Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw:
A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46 - 2004
- [j1]Sarvesh H. Kulkarni, Dennis Sylvester:
High performance level conversion for dual VDD design. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 926-936 (2004) - [c3]Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester:
A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205 - 2003
- [c2]Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni:
Pushing ASIC performance in a power envelope. DAC 2003: 788-793 - [c1]Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw:
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
Coauthor Index
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