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CICC 2001: San Diego, CA, USA
- Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, CICC 2001, San Diego, CA, USA, May 6-9, 2001. IEEE 2001, ISBN 0-7803-6591-7
- Atsushi Yoshizawa, Yannis P. Tsividis:
An anti-blocker structure MOSFET-C filter for a direct conversion receiver. 5-8 - Saska Lindfors, Tuomas Hollman, Teemu Salo, Kari Halonen:
A 2.7 V CMOS GSM/WCDMA continuous-time filter with automatic tuning. 9-12 - Daniel Senderowicz, Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto:
Embedded anti-aliasing in switched-capacitor ladder filters. 13-16 - Lei Wang, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
1.5 V 5.0 MHz switched capacitor circuits in 1.2 μm CMOS without voltage bootstrapper. 17-20 - Jorge Grilo, Ian Galton, Kevin Wang, Raymond Montemayor:
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. 23-26 - Khiem Nguyen, Bob Adams, Karl Sweetland:
A 105 dB SNR multibit ΣΔ ADC for digital audio applications. 27-30 - Ovidiu Bajdechi, Johan H. Huijsing:
A 1.8 V ΔΣ modulator interface for electret microphone with on-chip reference. 31-34 - Jens Sauerbrey, Roland Thewes:
Ultra low voltage switched opamp ΣΔ modulator for portable applications. 35-38 - Charvaka Duvvury:
ESD protection device issues for IC designs. 41-48 - Bo Shi, Lars Sundström
:
An IF CMOS signal component separator chip for LINC transmitters. 49-52 - Vladimir Aparin:
Accurate prediction of spectral regrowth and in-channel distortion based on CDMA signal time-domain model. 53-56 - Ichiro Aoki, Scott D. Kee, David B. Rutledge, Ali Hajimiri:
A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier. 57-60 - Steven J. E. Wilton, Resve Saleh:
Programmable logic IP cores in SoC design: opportunities and challenges. 63-66 - Theodore Vaida:
PLC advanced technology demonstrator TestChipB. 67-70 - Frank Lien, Jason Feng, Eddy Huang, Chung Sun, Tong Liu, Naihui Liao, David Hightower:
A hardware/software solution for embeddable FPGA. 71-74 - Steven W. Oldridge, Steven J. E. Wilton:
A novel FPGA architecture supporting wide shallow memories. 75-78 - Radim Cmar, Robert Pasko, Jean-Yves Mignolet, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde:
Platform design approach for re-configurable network appliances. 79-82 - Ashoke Rave, L. Rick Carley:
Mixed-swing methodology for domino logic circuits. 85-88 - Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda:
Utilizing surplus timing for power reduction. 89-92 - Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi
VTH-hopping scheme for 82% power saving in low-voltage processors. 93-96 - Ludovic Alvado, Jean Tomas, Sylvie Renaud-Le Masson, Vincent Douence:
Design of an analogue ASIC using subthreshold CMOS transistors to model biological neurons. 97-100 - Wim Claes, Willy Sansen, Robert Puers
A 40 μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants. 101-104 - John Doyle:
High sensitivity silicon magnetic field detector. 105-108 - Pierre-François Ruedi, Pascal Heim, Alessandro Mortara, Edoardo Franzi, Henri Oguey, Xavier Arreguit:
Interface circuit for metal-oxide gas sensor. 109-112 - Hubert Weinberger, Andreas Wiesbauer, Christian Fleischhacker, Joerg Hauptmann:
A 800 mW, full-rate ADSL-RT analog frontend IC with integrated line driver. 115-118 - Iuri Mehr, Prabir C. Maulik, Donald Paterson:
A 12-bit integrated analog front-end for broadband wireline networks. 119-122 - David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS. 123-126 - M. Altmann, J. M. Caia, R. Morle, Michael Dunsmore, Y. Xie, Namik Kocaman:
A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre. 127-130 - Tai-Cheng Lee, Behzad Razavi:
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. 131-134 - Scott D. Huss, Mark Mullen, C. Thomas Gray, Randall Smith, Mark Summers, Jeff Shafer, Pat Heron, Tim Sawinska, Joe Medero:
A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology. 135-138 - Robert C. Taft, Maria Rosaria Tursi, Andrew Glenny:
Design techniques for very low power ADCs. 141-144 - Conor Donovan, Michael P. Flynn:
A 'digital' 6-bit ADC in 0.25 μm CMOS. 145-148 - Baiying Yu, William C. Black Jr.:
A 900 MS/s 6b interleaved CMOS flash ADC. 149-152 - Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan:
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. 153-156 - Marc Borremans, Anne Van den Bosch, Michiel Steyaert
A low power, 10-bit CMOS D/A converter for high speed applications. 157-160 - Mohsen Moussavi, Ralph Mason, Calvin Plett:
A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD. 161-164 - Jiandong Jiang, Edward K. F. Lee:
A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter. 165-168 - Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada:
FeRAM device and circuit technologies fully compatible with advanced CMOS. 171-178 - Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi:
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip. 179-182 - Thomas Chadwick, Tarl Gordon, Rahul Nadkarni, Jeremy Rowland:
An ASIC-embedded content addressable memory with power-saving and design for test features. 183-186 - Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka:
A shared built-in self-repair analysis for multiple embedded memories. 187-190 - Michael R. Ouellette, Darren Anand, Peter Jakobsen:
Shared fuse macro for multiple embedded memory devices with redundancy. 191-194 - Pietro Andreani, Henrik Sjöland
A 2.2 GHz CMOS VCO with inductive degeneration noise suppression. 197-200 - Carlo Samori, Salvatore Levantino, Vito Boccuzzi:
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. 201-204 - Seong-Mo Yim, Kenneth K. O:
Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO. 205-208 - Alfio Zanchi, Andrea Bonfanti, Salvatore Levantino
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. 209-212 - Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. 213-216 - Anne Spataro, Yann Deval, Jean-Baptiste Bigueret, Pascal Fouillat, Didier Belot:
A CMOS VLSI delay oriented waveform converter dedicated to the synthesizer of an UMTS transceiver. 217-220 - Sani R. Nassif:
Modeling and analysis of manufacturing variations. 223-228 - Keith A. Bowman, James D. Meindl:
Impact of within-die parameter fluctuations on future maximum clock frequency distributions. 229-232 - Amir H. Ajami, Massoud Pedram, Kaustav Banerjee:
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs. 233-236 - Howard H. Smith, Aline Deutsch, Sharad Mehrotra, David Widiger, Michael A. Bowen, Allan H. Dansky, Gerard V. Kopcsay, Byron Krauter:
R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip. 237-240 - Yi-Chang Lu
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. 241-244 - Haitian Hu, Sachin S. Sapatnekar:
Circuit-aware on-chip inductance extraction. 245-248 - Nazmy Abaskharoun, Gordon W. Roberts:
Circuits for on-chip sub-nanosecond signal capture and characterization. 251-254 - Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy:
Effect of RTL coding style on testability. 255-258 - Shivakumar Swaminathan, Krishnendu Chakrabarty
A deterministic scan-BIST architecture with application to field testing of high-availability systems. 259-262 - Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu:
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems. 263-266 - Hisuko Sato, Mariko Ohtsuka, Kazumasa Yanagisawa, Peter M. Lee:
An efficient method of applying hot-carrier reliability simulation to logic design. 267-270 - Patrick McNamara, Sharad Saxena, Carlo Guardiani, Hideki Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, Kenichi Sugawara, Takeshi Matsunaga:
Design for manufacturability characterization and optimization of mixed-signal IP. 271-274 - Tamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori:
Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. 275-278 - Kamran Azadet, Erich Haratsch, Helen Kim, Fadi Saibi
DSP techniques for optical transceivers. 281-288 - Katsutoshi Seki, Kousuke Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama:
Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder. 289-292 - Chris J. Howland, Andrew J. Blanksby:
A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder. 293-296 - Jonathan B. Ashbrook, Naresh R. Shanbhag, Ralf Koetter, Richard E. Blahut:
Implementation of a Hermitian decoder IC in 0.35 μm CMOS. 297-300 - Marko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen:
A multicarrier QAM-modulator for WCDMA basestation with on-chip D/A converter. 301-304 - Thomas Richter, Wolfram Drescher, Frank Engel, S. Kobayashi, Vladimir Nikolajevic, Matthias Weiss, Gerhard P. Fettweis:
A platform-based highly parallel digital signal processor. 305-308 - Rajamohana Hegde, Naresh R. Shanbhag:
A low-power digital filter IC via soft DSP. 309-312 - Behzad Razavi:
Design of high-speed circuits for optical communication systems. 315-322 - Johan van der Tang, Dieter Kasperkovitz, Arthur H. M. van Roermund:
A 9.8-11.5 GHz quadrature ring oscillator for optical receivers. 323-326 - Lizhong Sun, Dale Nelson:
A 1.0 V GHz range 0.13 μm CMOS frequency synthesizer. 327-330 - Sorin P. Voinigescu, P. Popescu, P. Banens, Miles Copeland, G. Fortier, K. Howlett, M. Herod, David Marchesan, Jonathan L. Showell, S. Sziiagyi, Hai Tran, J. Weng:
Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s. 331-338 - Koen Uyttenhove, Michiel Steyaert
Speed-power-accuracy trade-off in high-speed ADCs: what about nano-electronics? 341-344 - Kevin G. Gard, Lawrence E. Larson, Michael B. Steer:
Autocorrelation analysis of distortion generated from bandpass nonlinear circuits. 345-348 - Kenneth Francken, Martin Vogels, Georges G. E. Gielen
Dedicated system-level simulation of ΔΣ modulators. 349-352 - Jerry D. Hayes, Larry Wissel:
Behavioral modeling for timing, noise, and signal integrity analysis. 353-356 - Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. 357-360 - Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich:
A fast method for identifying matching-relevant transistor pairs. 361-364 - Roberto Aparicio, Ali Hajimiri
Capacity limits and matching properties of lateral flux integrated capacitors. 365-368 - Elmar Gondro, Oskar Kowarik, Gerhard Knoblinger, Peter Klein:
When do we need non-quasistatic CMOS RF-models? 377-380 - Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu:
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. 381-384 - Jeffrey A. Babcock, Bill Loftin, Praful Madhani, Xinfen Chen, Angelo Pinto, Dieter K. Schroder:
Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technology. 385-388 - Simona Donati Guerrieri
A new analytical model for high frequency MOSFET noise. 389-392 - Zhaofeng Zhang, Jack Lau:
Experimental study on MOSFET's flicker noise under switching conditions and modelling in RF applications. 393-396 - Federica Cappelluti, Fabrizio Bonani
A new dynamic, self-consistent electro-thermal model of power HBTs and a novel interpretation of thermal collapse loci in multi-finger devices. 397-400 - Daniel Kehrer, Werner Simbürger, Hans-Dieter Wohlmuth, Arpad L. Scholtz:
Modeling of monolithic lumped planar transformers up to 20 GHz. 401-404 - William T. Cochran:
Successful modular process technology for system-on-a-chip applications. 407-412 - Maximilian Sergio, Nicolò Manaresi, Marco Tartagni, Roberto Canegallo, Roberto Guerrieri:
A system-on-chip for pressure-sensitive fabric. 413-416 - Vinod Nair, Martin Erdmann, Shridhar Mubaraq Mishra, Juraj Povazanec, Amit Shaligram, Chun Feng Hu:
A single chip terminal solution for high-end telephone applications. 417-420 - Yasuhiro Nakatsuka, Tetsuya Shhomura, Yuichiro Morita, Kazuhisa Takami, Manabu Joh, Masahisa Narita, Kazushige Yamagishi, Yutaka Okada, Jun Satoh:
A one chip super graphics CPU with direct unified memory controller suitable for car information and control system. 421-423 - Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Yusuke Kanehira, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuva Matsumura:
A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system. 425-428 - Christian Duerdodt, Martin Friedrich, Christian Grewing, Markus Hammes, Andre Hanke, Stefan Heinen, Jürgen Oehm
The first near zero-IF RX, 2-point modulation TX CMOS SOC Bluetooth solution. 429-432 - Diederik Verkest, Wolfgang Eberle, Patrick Schaumont, Bert Gyselinckx, Serge Vemalde:
C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN. 433-439 - Asad A. Abidi:
Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICE. 443-450 - N. Fujii, M. Kuraishi, T. Mochizuki, S. Irikuraz, T. Hirose:
A SOI-BiCMOS 800 Mbps write driver for hard disk drives. 451-454 - Bahram Zand, Khoman Phang, David A. Johns:
A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications. 455-458 - Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz. 459-462 - Andrea Pierazzi, Andrea Boni, Carlo Morandi:
Band-gap references for near 1-V operation in standard CMOS technology. 463-466 - Troy Stockstad, Hirokazu Yoshizawa:
A 0.9 V, 0.51 μA rail-to-rail CMOS operational amplifier. 467-470 - Wolfgang Roethig:
Coherent functional, electrical and physical modeling of IP blocks using ALF. 473-480 - Jean-Baptiste Bégueret, Yann Deval
Clock generator using factorial DLL for video applications. 485-488 - Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu:
A fast-lock mixed-mode DLL using a 2-b SAR algorithm. 489-492 - Haigang Feng, Ke Gong, Albert Z. Wang:
An ESD protection circuit for mixed-signal ICs. 493-496 - Vladimir I. Prodanov, Vito Boccuzzi:
7V tristate-capable output buffer implemented in standard 2.5 V CMOS process. 497-500 - Fumitoshi Hatori, Shouhei Kousai, Yasuo Unekawa:
Shared data line technique for doubling the data transfer rate per pin of differential interfaces. 501-504 - Delbert Cecchi, Charles Hanson, Curtis Preuss:
A 2 GB/s high speed link with differential simultaneous bi-directional IO. 505-508 - Armin Splett, Hans-Joachim Dreßler, Armin Fuchs, Ralf Hofmann, Björn Jelonnek, Helmut Kling, Eric Koenig, Anton Schultheiß:
Solutions for highly integrated future generation software radio basestation transceivers. 511-518 - Salvatore Cosentino, Pietro Filoramo, Angelo Granata, Marco Marletta, Giuseppe Martino, Roberto Pelleriti, Felice Torrisi, Mario Paparo, Gaetano Cosentino, Paolo Vita, Giuseppe Palmisano:
An integrated RF transceiver for DECT application. 519-522 - Hooman Darabi, Shahla Khorram, Brima Ibrahim, Maryam Rofougaran, Ahmadreza Rofougaran:
An IF FSK demodulator for Bluetooth in 0.35 μm CMOS. 523-526 - Carl J. Debono
A 900 MHz, 0.9 V low-power CMOS downconversion mixer. 527-530 - Xi Li, Tom Brogan, Mark Esposito, Brent Myers, Kenneth K. O:
A comparison of CMOS and SiGe LNA's and mixers for wireless LAN application. 531-534 - Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano:
Interface socket design methodology to generate embedded DRAM macros. 537-540 - Thomas E. Bonnerud, Bjørnar Hernes, Trond Ytterdal:
A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications. 541-544 - W. Rhett Davis
A design environment for high throughput, low power dedicated signal processing systems. 545-548 - Shunzo Yamashita, Hidetoshi Chikata, Yuji Onishi, Naoki Kato, Tom Hiyama, Kazuo Yano:
RTL morphing: making IP-reuse work in system-on-a-chip designs. 549-552 - Youngsoo Shin, Hiroshi Kawaguchi
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. 553-556 - Seshadri Subbanna, Lawrence Larson, Greg G. Freeman, David Ahlgren, Kenneth J. Stein, Carl E. Dickey, James Mecke, A. Rincon, P. Bacon, Robert A. Groves, Mehmet Soyuer, David L. Harame, James S. Dunn, David Rowe, W. Chon, Dean A. Herman Jr., Bernard S. Meyerson:
Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs. 559-566 - Bernd-Ulrich H. Klepser, Markus Scholz, Wolfgang Klein:
A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer. 567-570 - Kok Wai Johnny Chew, Shao-Fu Sanford Chu, Che Choi Chester Leung:
Driving CMOS into the wireless communications arena with technology scaling. 571-574 - John W. M. Rogers, Vladislav Levenets, Chris A. Pawlowicz, N. Garry Tarr, Tom J. Smy, Calvin Plett:
A completely integrated 2 GHz VCO with post-processed Cu inductors. 575-578 - Hasnain Lakdawala, Xu Zhu, Hao Luo, Suresh Santhanam, L. Rick Carley, Gary K. Fedder:
Micromachined high-Q inductors in 0.18 μm Cu interconnect low-K CMOS. 579-582
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