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Koichi Nose
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2020 – today
- 2024
- [c18]Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi:
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications. ISSCC 2024: 364-366
2010 – 2019
- 2019
- [c17]Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose:
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. VLSI Circuits 2019: 248- - 2015
- [c16]Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose:
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels. ISSCC 2015: 1-2 - [c15]Jan Genoe
, Koichi Nose:
Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee. ISSCC 2015: 288-289 - 2012
- [j9]Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits 47(4): 832-840 (2012) - [c14]Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno:
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC 2012: 16-17 - 2010
- [j8]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda:
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45(10): 2057-2065 (2010) - [c13]Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno:
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC 2010: 192-193
2000 – 2009
- 2009
- [j7]Keishi Ohashi
On-Chip Optical Interconnect. Proc. IEEE 97(7): 1186-1198 (2009) - [c12]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno:
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471 - 2008
- [j6]Junichi Fujikata
LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Trans. Electron. 91-C(2): 131-137 (2008) - [j5]Koichi Nose, Masayuki Mizuno:
A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. IEEE J. Solid State Circuits 43(4): 1038-1046 (2008) - 2007
- [c11]Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. ISSCC 2007: 66-587 - [c10]Toru Nakura, Koichi Nose, Masayuki Mizuno:
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC 2007: 402-611 - 2006
- [j4]Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits 41(12): 2911-2920 (2006) - [c9]Keishi Ohashi
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC 2006: 1686-1695 - [c8]Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC 2006: 2112-2121 - 2004
- [c7]Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka
Frequency-hopping vernier clock generators for multiple clock domain SoCs. CICC 2004: 91-94 - 2002
- [j3]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi
VTH-hopping scheme to reduce subthreshold leakage for low-power processors. IEEE J. Solid State Circuits 37(3): 413-419 (2002) - [c6]Koichi Nose, Takayasu Sakurai:
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29 - 2001
- [c5]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi
VTH-hopping scheme for 82% power saving in low-voltage processors. CICC 2001: 93-96 - [c4]Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai:
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286 - 2000
- [j2]Hiroshi Kawaguchi
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits 35(10): 1498-1501 (2000) - [j1]Koichi Nose, Takayasu Sakurai:
Analysis and future trend of short-circuit power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1023-1030 (2000) - [c3]Koichi Nose, Takayasu Sakurai:
Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474 - [c2]Koichi Nose, Soo-Ik Chae, Takayasu Sakurai:
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230
1990 – 1999
- 1998
- [c1]Koichi Nose, Takayasu Sakurai:
Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326
Coauthor Index
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