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Takeo Yamashita
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2010 – 2019
- 2016
- [c5]Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. ISSCC 2016: 60-61 - 2015
- [c4]Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. ISSCC 2015: 1-3
2000 – 2009
- 2001
- [c3]Tamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori:
Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. CICC 2001: 275-278
1990 – 1999
- 1995
- [c2]Tadashi Shibata, Tsutomu Nakai, Tatsuo Morimoto, Ryu Kaihara, Takeo Yamashita, Tadahiro Ohmi:
Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. NIPS 1995: 685-691 - 1993
- [c1]Tadashi Shibata, Koji Kotani, Takeo Yamashita, Hiroshi Ishii, Hideo Kosaka, Tadahiro Ohmi:
Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. NIPS 1993: 919-926
Coauthor Index
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