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Lars Sundström
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2020 – today
- 2023
- [c32]Mattias Palm, Daniele Mastantuono, Christer Jansson, Erik Backenius, Nikola Ivanisevic, Mikael Normark, Prakash Harikumar, My-Chien Yee, Andreas Leidenhed, Roland Strandberg, Sunny Sharma
, Hanie Ghaedrahmati, Martin Anderson, Peter Nygren, Peter Sjögren, Erik Säll, Robert Hägglund, Lars Sundström
A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. ESSCIRC 2023: 333-336 - 2022
- [c31]Staffan Ek, Patrik Karlsson, Andreas Kämpe, Roland Strandberg, Aravind Tharayil Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, Nikola Ivanisevic, Robert Nilsson, Peter Nygren, Mattias Palm, Erik Säll, Sha Tao, My-Chien Yee, Lars Sundström
A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. ESSCIRC 2022: 237-240 - 2020
- [c30]Siyu Tan, Daniele Mastantuono, Roland Strandberg, Lars Sundström
A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration. ISCAS 2020: 1-5 - [c29]Siyu Tan, Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström
A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs. NorCAS 2020: 1-6
2010 – 2019
- 2019
- [c28]Siyu Tan, Lars Sundström
A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. NORCAS 2019: 1-4 - 2018
- [j10]Staffan Ek, Tony Påhlsson
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers. IEEE J. Solid State Circuits 53(7): 1988-2000 (2018) - 2017
- [c27]Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström
A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI. ESSCIRC 2017: 179-180 - [c26]Christian Elgaard, Lars Sundström
A 491.52 MHz 840 uW crystal oscillator in 28 nm FD-SOI CMOS for 5G applications. ESSCIRC 2017: 247-250 - 2016
- [j9]Ali A. Zaidi, Robert Baldemair, Hugo M. Tullberg, Hakan Bjorkegren, Lars Sundström
Waveform and Numerology to Support 5G Services and Requirements. IEEE Commun. Mag. 54(11): 90-98 (2016) - [j8]Xiaodong Liu, Anders Nejdel, Mattias Palm, Lars Sundström
A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters. IEEE J. Solid State Circuits 51(7): 1566-1578 (2016) - 2015
- [c25]Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström
A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters. ESSCIRC 2015: 299-302 - 2014
- [j7]Mattias Andersson, Martin Anderson, Lars Sundström
A Filtering ΔΣ ADC for LTE and Beyond. IEEE J. Solid State Circuits 49(7): 1535-1547 (2014) - [c24]Xiaodong Liu, Mattias Andersson, Martin Anderson, Lars Sundström
An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS. ISCAS 2014: 2337-2340 - [c23]Dejan Radjen, Martin Anderson, Lars Sundström
A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer. NORCHIP 2014: 1-4 - 2013
- [j6]Chester Sungchung Park, Lars Sundström
Carrier aggregation for LTE-advanced: design challenges of terminals. IEEE Commun. Mag. 51(12): 76-84 (2013) - [j5]Lars Sundström
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. IEEE J. Solid State Circuits 48(7): 1659-1668 (2013) - [c22]Mattias Andersson, Martin Anderson, Lars Sundström
A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression. ESSCIRC 2013: 323-326 - [c21]Lars Sundström
A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. ISSCC 2013: 336-337 - [c20]Dejan Radjen, Pietro Andreani, Martin Anderson, Lars Sundström
A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier. NORCHIP 2013: 1-4 - [c19]Leif R. Wilhelmsson, Jim Svensson, Martin Anderson, Staffan Ek, Roland Strandberg, Lars Sundström
Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation. VTC Spring 2013: 1-5 - 2012
- [c18]Lars Sundström
Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS. ESSCIRC 2012: 357-360 - [c17]Martin Anderson, Roland Strandberg, Staffan Ek, Leif R. Wilhelmsson, Lars Sundström
A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. ESSCIRC 2012: 470-473 - 2011
- [c16]Magnus Nilsson, Sven Mattisson, Nikolaus Klemmer, Martin Anderson, Torkel Arnborg, Peter Caputa, Staffan Ek, Lin Fan, Henrik Fredriksson, Fabien Garrigues, Henrik Geis, Hans Hagberg, Joel Hedestig, Hu Huang, Yevgeniy Kagan, Niklas Karlsson, Henrik Kinzel, Thomas Mattsson, Thomas Mills, Fenghao Mu, Andreas Mårtensson, Lars Nicklasson, Filip Oredsson, Ufuk Ozdemir, Fitzgerald Park, Tony Pettersson, Tony Påhlsson, Markus Pålsson, Stephane Ramon, Magnus Sandgren, Per Sandrup, Anna-Karin Stenman, Roland Strandberg, Lars Sundström
A 9-band WCDMA/EDGE transceiver supporting HSPA evolution. ISSCC 2011: 366-368 - [c15]Dejan Radjen, Pietro Andreani, Martin Anderson, Lars Sundström
A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback. NORCHIP 2011: 1-4 - [c14]Leif R. Wilhelmsson, Fenghao Mu, Lars Sundström
Simultaneous Reception and Scanning Using Complex IF Radio Architectures. VTC Fall 2011: 1-5 - 2010
- [c13]Mattias Andersson, Martin Anderson, Pietro Andreani, Lars Sundström
Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators. ISCAS 2010: 4021-4024
2000 – 2009
- 2009
- [j4]Martin Anderson, Lars Sundström
Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback. IEEE J. Solid State Circuits 44(2): 473-483 (2009) - [j3]Martin Anderson, Lars Sundström
DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 530-534 (2009) - 2007
- [c12]Martin Anderson, Lars Sundström
A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current. ESSCIRC 2007: 240-243 - 2003
- [c11]Bo Shi, Lars Sundström
A time-continuous optimization method for automatic adjustment of gain and phase imbalances in feedforward and LINC transmitters. ISCAS (1) 2003: 45-48 - 2002
- [c10]Roland Strandberg, Pietro Andreani, Lars Sundström
Bandwidth considerations for a CALLUM transmitter architecture. ISCAS (4) 2002: 25-28 - [c9]L. Durkalec, Lars Sundström
Properties of RF bandpass amplifier topology with Q-enhancing. ISCAS (1) 2002: 529-532 - 2001
- [c8]Bo Shi, Lars Sundström
An IF CMOS signal component separator chip for LINC transmitters. CICC 2001: 49-52 - [c7]Bo Shi, Lars Sundström
Investigation of a highly efficient LINC amplifier topology. VTC Fall 2001: 1215-1219 - [c6]Weiyun Shan, Lars Sundström
Spectral sensitivity of predistortion linearizer architectures to filter ripple. VTC Fall 2001: 1570-1574 - 2000
- [j2]Bo Shi
A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters. IEEE J. Solid State Circuits 35(7): 987-993 (2000) - [j1]Lars Sundström
Spectral sensitivity of LINC transmitters to quadrature modulator misalignments. IEEE Trans. Veh. Technol. 49(4): 1474-1487 (2000) - [c5]Bo Shi, Lars Sundström
A novel design using translinear circuit for linear LINC transmitters. ISCAS 2000: 64-67
1990 – 1999
- 1999
- [c4]Anna-Karin Stenman, Lars Sundström
Extended analysis of input impedance control of an NMOS-transistor with an inductive series feedback. ICECS 1999: 307-310 - [c3]Eric Westesson, Lars Sundström
A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers. ISCAS (1) 1999: 206-209 - [c2]Bo Shi, Lars Sundström
Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers. ISCAS (2) 1999: 252-255 - [c1]Pietro Andreani, Lars Sundström
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier. ISCAS (1) 1999: 346-349
Coauthor Index
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