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Hideto Hidaka
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2020 – today
- 2020
- [j19]Takashi Kono, Yasuhiko Taito, Hideto Hidaka:
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age. IEICE Trans. Electron. 103-C(4): 132-143 (2020)
2010 – 2019
- 2019
- [j18]Hideto Hidaka:
Foreword. IEICE Trans. Electron. 102-C(4): 243-244 (2019) - [j17]Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka:
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. 102-C(4): 287-295 (2019) - 2018
- [j16]Hideto Hidaka:
Foreword. IEICE Trans. Electron. 101-C(4): 186 (2018) - [p2]Hideto Hidaka:
Introduction. Embedded Flash Memory for Embedded Systems 2018: 1-6 - [p1]Hideto Hidaka:
Applications and Technology Trend in Embedded Flash Memory. Embedded Flash Memory for Embedded Systems 2018: 7-27 - [e1]Hideto Hidaka:
Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Integrated Circuits and Systems, Springer 2018, ISBN 978-3-319-55305-4 [contents] - 2016
- [j15]Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits 51(1): 213-221 (2016) - [c12]Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. ISSCC 2016: 140-141 - 2015
- [c11]Hideto Hidaka:
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology. A-SSCC 2015: 1-4 - [c10]Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC 2015: 1-3 - 2014
- [j14]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. IEEE J. Solid State Circuits 49(1): 154-166 (2014) - 2013
- [c9]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. ISSCC 2013: 212-213 - 2012
- [c8]Anantha P. Chandrakasan, Hideto Hidaka:
Session 1 overview: Plenary session. ISSCC 2012: 7-9 - 2010
- [c7]Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai:
Silicon 3D-integration technology and systems. ISSCC 2010: 510-511
2000 – 2009
- 2009
- [j13]Donhee Ham
, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 44(1): 3-6 (2009) - 2007
- [c6]Hideto Hidaka, Yair Sofer:
Non-Volatile Memories. ISSCC 2007: 470-471 - 2002
- [j12]Hirohito Kikukawa, Shigeki Tomishima
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37(7): 932-940 (2002) - [c5]Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo:
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. ITC 2002: 170-177 - 2001
- [j11]Shigeki Tomishima
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. IEEE J. Solid State Circuits 36(11): 1728-1737 (2001) - [c4]Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka:
A shared built-in self-repair analysis for multiple embedded memories. CICC 2001: 187-190 - 2000
- [c3]Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka:
A built-in self-repair analyzer (CRESTA) for embedded DRAMs. ITC 2000: 567-574
1990 – 1999
- 1999
- [j10]Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34(8): 1084-1090 (1999) - 1996
- [j9]Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki:
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits 31(4): 575-585 (1996) - 1995
- [j8]Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki:
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. IEEE J. Solid State Circuits 30(4): 471-479 (1995) - 1994
- [j7]Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29(4): 432-440 (1994) - [j6]Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29(11): 1303-1309 (1994) - [j5]Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits 29(11): 1323-1329 (1994) - 1993
- [j4]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima:
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10(2): 6-12 (1993) - 1992
- [c2]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC 1992: 615-622 - 1990
- [j3]Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima:
The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro 10(2): 14-25 (1990)
1980 – 1989
- 1989
- [j2]Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara:
Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits 24(1): 21-27 (1989) - [j1]Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima:
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. IEEE J. Solid State Circuits 24(1): 43-49 (1989) - 1986
- [c1]Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka:
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. ITC 1986: 826-829
Coauthor Index
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