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Helmut E. Graeb
Helmut Graeb – Helmut Gräb
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- affiliation: Technical University Munich, Germany
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2020 – today
- 2023
- [c75]Helmut Graeb
, Markus Leibl
Learning from the Implicit Functional Hierarchy in an Analog Netlist. ISPD 2023: 93-100 - 2022
- [j30]Inga Abel
A functional block decomposition method for automatic op-amp design. Integr. 85: 108-120 (2022) - [j29]Inga Abel
A Hierarchical Performance Equation Library for Basic Op-Amp Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 1976-1989 (2022) - [j28]Inga Abel
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. ACM Trans. Design Autom. Electr. Syst. 27(6): 63:1-63:27 (2022) - [c74]Helmut Graeb:
Analog Synthesis - The Deterministic Way. ISPD 2022: 167-174 - 2021
- [j27]Inga Abel, Maximilian Neuner, Helmut Graeb:
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing. Integr. 76: 148-158 (2021) - [c73]Grace Li Zhang
An Efficient Programming Framework for Memristor-based Neuromorphic Computing. DATE 2021: 1068-1073 - [c72]Maximilian Neuner, Inga Abel, Helmut Graeb:
Library-free Structure Recognition for Analog Circuits. DATE 2021: 1366-1371 - [i3]Inga Abel, Helmut Graeb:
Structure Synthesis of Op-Amps by Functional Block Composition. CoRR abs/2101.07517 (2021) - 2020
- [j26]Bernhard Lippmann, Niklas Unverricht, Aayush Singla, Matthias Ludwig
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. Integr. 71: 11-29 (2020) - [j25]Maximilian Neuner, Helmut Graeb:
Verification and revision of the power-down mode for hierarchical analog circuits. Integr. 73: 1-9 (2020) - [j24]Ye X. Ding, Florin Burcea
PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1372-1385 (2020) - [j23]Jahnavi Kasturi Rangan
Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 401-414 (2020) - [c71]Maximilian Neuner, Helmut Graeb:
Synergetic Algorithm for Power-Down Synthesis. ECCTD 2020: 1-5 - [c70]Inga Abel, Helmut Graeb:
Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling. ICCAD 2020: 53:1-53:6 - [c69]Maximilian Neuner, Helmut Graeb:
Hierarchical Analog Power-Down Synthesis. ICECS 2020: 1-4 - [c68]Aayush Singla, Bernhard Lippmann, Helmut Graeb:
Recovery of 2D and 3D Layout Information through an Advanced Image Stitching Algorithm using Scanning Electron Microscope Images. ICPR 2020: 3860-3867 - [c67]Alessandro Girardi, Helmut Graeb:
Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement. SBCCI 2020: 1-6 - [i2]Inga Abel, Maximilian Neuner, Helmut Graeb:
A Functional Block Decomposition Method for Automatic Op-Amp Design. CoRR abs/2012.09051 (2020) - [i1]Inga Abel, Maximilian Neuner, Helmut Graeb:
A Hierarchical Performance Equation Library for Op-Amp Design. CoRR abs/2012.09088 (2020)
2010 – 2019
- 2019
- [j22]Vittorio Latorre
Derivative free methodologies for circuit worst case analysis. Optim. Lett. 13(7): 1557-1571 (2019) - [j21]Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb:
MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters. ACM Trans. Design Autom. Electr. Syst. 24(4): 43:1-43:24 (2019) - [c66]Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb:
Integrated flow for reverse engineering of nanoscale technologies. ASP-DAC 2019: 82-89 - [c65]Samarjit Chakraborty
Cross-Layer Interactions in CPS for Performance and Certification. DATE 2019: 1439-1444 - [c64]Inga Abel, Maximilian Neuner, Helmut Graeb:
Constraint-Programmed Initial Sizing of Analog Operational Amplifiers. ICCD 2019: 413-421 - [c63]Florin Burcea, Helmut Graeb:
Inversion-Coefficient-Aware Yield Optimization of Analog Circuits. ICECS 2019: 193-196 - [c62]Aayush Singla, Bernhard Lippmann, Helmut Graeb:
Verification of Physical Chip Layouts Using GDSII Design Data. IVSW 2019: 55-60 - [c61]Maximilian Neuner, Helmut Graeb:
Power-Down Mode Verification for Hierarchical Analog Circuits. SMACD 2019: 125-128 - [c60]Sebastian Kiesel, Thomas Kern, Bernhard Wicht, Helmut Graeb:
A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application. VLSI-DAT 2019: 1-4 - 2018
- [j20]Francesco Santoro
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications. IEEE J. Solid State Circuits 53(6): 1856-1868 (2018) - [c59]Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC 2018: 233-238 - [c58]Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb:
MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side. ICECS 2018: 625-628 - [c57]Jahnavi Kasturi Rangan, Nasim Pour Aryan, Lantao Wang
Design-dependent Monitors Based on Delay Sensitivity Tracking. ICECS 2018: 633-636 - [c56]Michael Werner, Bernhard Lippmann, Johanna Baehr
Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis. IVSW 2018: 13-18 - [c55]Andreas Herrmann, Michael Weiner, Michael Pehl, Helmut Graeb:
Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector. SMACD 2018: 1-4 - 2017
- [j19]Michael Zwerger, Maximilian Neuner
Analog Power-Down Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 1954-1967 (2017) - [j18]Pang-Yen Chou
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2234-2247 (2017) - [c54]Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. DATE 2017: 1757-1762 - [c53]Florin Burcea, Andreas Herrmann, Aditya Gupta, Helmut Graeb:
A new robustness optimization methodology for MEMS-IC systems. SMACD 2017: 1-4 - [c52]Andreas Herrmann, Christof Hielscher, Alexander Mueller, Gisbert Hoelzer, Helmut Graeb:
Realistic worst-case parameter sets for MEMS technologies. SMACD 2017: 1-4 - 2016
- [j17]Michael Pehl, Matthias Hiller
Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures. J. Circuits Syst. Comput. 25(1): 1640001:1-1640001:23 (2016) - [j16]Husni M. Habal, Helmut Graeb:
A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits. Microelectron. Reliab. 61: 17-23 (2016) - [j15]Mark Po-Hung Lin
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1229-1242 (2016) - [j14]Florin Burcea, Husni M. Habal, Helmut E. Graeb:
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1397-1410 (2016) - [c51]Florin Burcea, Husni M. Habal, Helmut E. Graeb:
Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. DAC 2016: 102:1-102:6 - [c50]Michael Zwerger, Gaurav Shrivastava, Helmut Graeb:
Power-down synthesis for analog circuits including switch sizing. SMACD 2016: 1-4 - 2015
- [c49]Michael Zwerger, Helmut E. Graeb:
Detection of asymmetric aging-critical voltage conditions in analog power-down mode. DATE 2015: 1269-1272 - [c48]Michael Zwerger, Maximilian Neuner, Helmut E. Graeb:
Power-Down Circuit Synthesis for Analog/Mixed-Signal. ICCAD 2015: 656-663 - [c47]Chia-Yu Wu, Helmut Graeb, Jiang Hu:
A pre-search assisted ILP approach to analog integrated circuit routing. ICCD 2015: 244-250 - [c46]Michael Zwerger, Pantelis-Rafail Vlachas
A fast analytical approach for static power-down mode analysis. ICECS 2015: 1-4 - 2014
- [c45]Michael Pehl, Akshara Ranjit Punnakkal, Matthias Hiller
Advanced performance metrics for Physical Unclonable Functions. ISIC 2014: 136-139 - 2013
- [c44]Veit Kleeberger
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. DAC 2013: 33:1-33:6 - [c43]Husni M. Habal, Helmut E. Graeb:
Evaluating analog circuit performance in light of MOSFET aging at different time scales. ICICDT 2013: 41-44 - 2012
- [j13]Michael Pehl, Helmut E. Graeb:
Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach. J. Circuits Syst. Comput. 21(8) (2012) - [j12]Xin Pan, Helmut Graeb:
Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area. Microelectron. Reliab. 52(8): 1559-1564 (2012) - [j11]Michael Eick, Helmut E. Graeb:
MARS: Matching-Driven Analog Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1145-1158 (2012) - [c42]Helmut Graeb:
ITRS 2011 Analog EDA Challenges and Approaches. DATE 2012: 1150-1155 - 2011
- [j10]Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 180-193 (2011) - [j9]Husni M. Habal, Helmut Graeb:
Constraint-Based Layout-Driven Sizing of Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1089-1102 (2011) - [e1]Joel R. Phillips, Alan J. Hu, Helmut Graeb:
2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1399-6 [contents] - 2010
- [c41]Xin Pan, Helmut Graeb:
Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction. CICC 2010: 1-4 - [c40]Daniel Mueller-Gritschneder
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. DATE 2010: 1088-1093 - [c39]Michael Pehl, Michael Zwerger, Helmut E. Graeb:
Sizing analog circuits using an SQP and Branch and Bound based approach. ICECS 2010: 37-40 - [c38]Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann
Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD 2010: 47-54 - [c37]Xin Pan, Helmut Graeb:
Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate. ISQED 2010: 861-865
2000 – 2009
- 2009
- [j8]Helmut Graeb, Daniel Mueller-Gritschneder
Pareto optimization of analog circuits considering variability. Int. J. Circuit Theory Appl. 37(2): 283-299 (2009) - [j7]Daniel Mueller-Gritschneder
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. SIAM J. Optim. 20(2): 915-934 (2009) - [c36]Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser:
Analog layout synthesis - Recent advances in topological approaches. DATE 2009: 274-279 - [c35]Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang:
Formal approaches to analog circuit verification. DATE 2009: 724-729 - [c34]Engin Avci, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
A free-shape router for analog and RF applications. ECCTD 2009: 771-774 - [c33]Xin Pan, Helmut Graeb:
Degradation-aware analog design flow for lifetime yield analysis and optimization. ICECS 2009: 667-670 - 2008
- [j6]Tobias Massier
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2209-2222 (2008) - [c32]David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
From Transistor to PLL - Analogue Design and EDA Methods. DATE 2008 - [c31]Tobias Massier
Sizing Rules for Bipolar Analog Circuit Design. DATE 2008: 140-145 - [c30]Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. ICCAD 2008: 306-313 - [c29]Michael Pehl, Tobias Massier
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD 2008: 188-193 - 2007
- [j5]Guido Stehr, Helmut E. Graeb, Kurt Antreich:
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1733-1748 (2007) - [c28]Jun Zou, Helmut Graeb, Daniel Mueller
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. CICC 2007: 607-610 - [c27]Daniel Mueller
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE 2007: 75-80 - [c26]Helmut Graeb, Daniel Mueller
Pareto optimization of analog circuits considering variability. ECCTD 2007: 28-31 - [c25]Jun Zou, Daniel Mueller
Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED 2007: 481-486 - 2006
- [c24]Jun Zou, Daniel Mueller
A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC 2006: 19-24 - [c23]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
Fast evaluation of analog circuit structures by polytopal approximations. ISCAS 2006 - 2005
- [c22]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
Deterministic approaches to analog performance space exploration (PSE). DAC 2005: 869-874 - [c21]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann:
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) 2005: 334-338 - 2004
- [c20]Guido Stehr, Helmut E. Graeb, Kurt Antreich:
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ICCAD 2004: 847-854 - 2003
- [c19]Guido Stehr, Helmut E. Graeb, Kurt Antreich:
Performance trade-off analysis of analog circuits by normal-boundary intersection. DAC 2003: 958-963 - [c18]Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD 2003: 241-246 - 2002
- [c17]Michael Pronath, Helmut E. Graeb, Kurt Antreich:
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. DATE 2002: 78-83 - [c16]Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb:
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE 2002: 581-585 - 2001
- [c15]Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich:
A fast method for identifying matching-relevant transistor pairs. CICC 2001: 361-364 - [c14]Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich:
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC 2001: 858-863 - [c13]Helmut E. Graeb, Stephan Zizala, Josef Eckmüller, Kurt Antreich:
The Sizing Rules Method for Analog Integrated Circuit Design. ICCAD 2001: 343-349 - 2000
- [c12]Kurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala:
WiCkeD: analog circuit synthesis incorporating mismatch. CICC 2000: 511-514 - [c11]Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE 2000: 42-47 - [c10]Michael Pronath, Volker Gloeckel, Helmut E. Graeb:
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. ICCAD 2000: 557-561
1990 – 1999
- 1999
- [j4]Michael Pronath, Volker Glöckel, Helmut Gräb, Kurt Antreich:
Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme. Informationstechnik Tech. Inform. 41(2): 42-45 (1999) - [j3]Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich:
Analog testing by characteristic observation inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1353-1368 (1999) - [c9]Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich:
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. DATE 1999: 323-327 - 1998
- [c8]Josef Eckmüller, Martin Groepl, Helmut E. Graeb:
Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE 1998: 636-643 - [c7]Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb:
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. DATE 1998: 822-827 - [c6]Stephan Zizala, Josef Eckmüller, Helmut Gräb:
Fast calculation of analog circuits' feasibility regions by low level functional measures. ICECS 1998: 85-88 - 1995
- [c5]Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich:
Design based analog testing by Characteristic Observation Inference. ICCAD 1995: 620-626 - 1994
- [j2]Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser:
Circuit analysis and optimization driven by worst-case distances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 57-71 (1994) - [c4]Wolfgang T. Eisenmann, Helmut E. Graeb:
Fast transient power and noise estimation for VLSI circuits. ICCAD 1994: 252-257 - 1993
- [b1]Helmut Gräb:
Schaltkreisoptimierung mit Worst-Case-Abständen als Zielgrössen. Technical University Munich, Germany, Shaker 1993, ISBN 978-3-86111-658-5, pp. 1-115 - [c3]Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich:
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. DAC 1993: 142-147 - 1992
- [j1]Helmut E. Graeb, Reiner E. Lederle:
Circuit yield optimization by analyzing performance statistics. Microprocess. Microprogramming 35(1-5): 697-703 (1992) - [c2]Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich:
Design verification considering manufacturing tolerances by using worst-caste distances. EURO-DAC 1992: 86-91 - 1991
- [c1]Kurt Antreich, Helmut E. Graeb:
Circuit Optimization Driven by Worst-Case Distances. ICCAD 1991: 166-169
Coauthor Index
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