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Kamran Azadet
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2020 – today
- 2021
- [j8]Daniel Gruber
, Martin Clara
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. IEEE J. Solid State Circuits 56(12): 3655-3667 (2021) - [c19]Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet:
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. ISSCC 2021: 174-176 - [c18]Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet:
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. ISSCC 2021: 176-178 - [c17]Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet:
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. ISSCC 2021: 451-453
2010 – 2019
- 2015
- [j7]Taesong Hwang, Kamran Azadet, Ross S. Wilson, Jenshan Lin
Nonlinearity Modeling of a Chireix Outphasing Power Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2898-2907 (2015) - [c16]Rui Wang, Yang You, Guoying Wu
A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. MWSCAS 2015: 1-4 - 2012
- [c15]Rui Wang, Xiaoke Wen, Kamran Azadet, Changzhi Li
A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS. ISCAS 2012: 305-308
2000 – 2009
- 2007
- [c14]Meng Yu, Jing (Tiffany) Li, Rick S. Blum, Kamran Azadet:
Toward Maximizing Throughput in Wireless Relay: A General User Cooperation Model. CISS 2007: 25-30 - 2006
- [j6]Jinghong Chen, Fadi Saibi
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication. IEEE J. Solid State Circuits 41(8): 1876-1893 (2006) - 2005
- [c13]Jinghong Chen, Fadi Saibi
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system. CICC 2005: 135-138 - 2003
- [c12]Guillaume Ding, Catherine Dehollain, Michel J. Declercq, Kamran Azadet:
Frequency-interleaving technique for high-speed A/D conversion. ISCAS (1) 2003: 857-860 - 2002
- [j5]Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi
Equalization and FEC techniques for optical transceivers. IEEE J. Solid State Circuits 37(3): 317-327 (2002) - [c11]Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.:
A low power adaptive filter using dynamic reduced 2's-complement representation. CICC 2002: 141-144 - [c10]Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.:
The use of reduced two's-complement representation in low-power DSP design. ISCAS (1) 2002: 77-80 - 2001
- [j4]Erich F. Haratsch, Kamran Azadet:
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. IEEE J. Solid State Circuits 36(3): 374-384 (2001) - [c9]Kamran Azadet, Erich Haratsch, Helen Kim, Fadi Saibi
DSP techniques for optical transceivers. CICC 2001: 281-288 - 2000
- [c8]Erich F. Haratsch, Kamran Azadet:
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. CICC 2000: 465-468 - [c7]Erich F. Haratsch, Kamran Azadet:
Pipelined reduced-state sequence estimation. GLOBECOM 2000: 1046-1050 - [c6]Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet:
Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. ICC (1) 2000: 372-376 - [c5]Erich F. Haratsch, Kamran Azadet:
High-speed reduced-state sequence estimation. ISCAS 2000: 387-390
1990 – 1999
- 1998
- [j3]Kamran Azadet, Chris J. Nicole:
Low-power equalizer architectures for high-speed modems. IEEE Commun. Mag. 36(10): 118-126 (1998) - [j2]Marc J. Loinaz, Kanwar Jit Singh, Andrew J. Blanksby, David A. Inglis, Kamran Azadet, Bryan D. Ackland:
A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s. IEEE J. Solid State Circuits 33(12): 2092-2103 (1998) - [c4]Tracy C. Denk, Chris J. Nicol, Patrik Larsson, Kamran Azadet:
Reconfigurable hardware for efficient implementation of programmable FIR filters. ICASSP 1998: 3005-3008 - 1997
- [j1]Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill:
A low-power 128-tap digital adaptive equalizer for broadband modems. IEEE J. Solid State Circuits 32(11): 1777-1789 (1997) - 1995
- [c3]Kamran Azadet, Alex G. Dickinson, David A. Inglis:
A Mismatch-Free CMOS Dynamic Voltage Comparator. ISCAS 1995: 2116-2119 - 1994
- [c2]F. Yang, PatrickSenn Loumeaeu, Kamran Azadet, P. Senn:
The Design of CMOS Transconductor for High Frequency Continuous-Time Filter Applications. ISCAS 1994: 513-516 - [c1]Kamran Azadet, J. Porte, F. Yang, J. E. D. Hurwitz:
Mixed-Mode Continuous-Time Video Acquisition Filters. ISCAS 1994: 775-778
Coauthor Index
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