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Shinji Miyano
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2020 – today
- 2024
- [c20]Shinichi Sasaki, Yuta Aiba, Yusuke Komano, Takahiko Iizuka, Motohiko Fujimatsu, Atsushi Kawasumi, Daisuke Miyashita, Jun Deguchi, Takashi Maeda, Shinji Miyano, Tooru Maruyama:
Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI. NewCAS 2024: 238-242
2010 – 2019
- 2014
- [c19]Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, Takehiko Hojo:
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. ISSCC 2014: 236-237 - 2013
- [j13]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto:
NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM. IEICE Trans. Electron. 96-C(5): 620-623 (2013) - [j12]Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano:
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress. IEICE Trans. Electron. 96-C(6): 759-765 (2013) - [j11]Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara:
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits 48(4): 924-931 (2013) - [j10]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits 48(9): 2239-2249 (2013) - [c18]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 - [c17]Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC 2013: 1-4 - 2012
- [j9]Shusuke Yoshimoto
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012) - [j8]Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. IEICE Trans. Electron. 95-C(4): 564-571 (2012) - [j7]Shusuke Yoshimoto
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012) - [j6]Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi:
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1635-1643 (2012) - [c16]Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara:
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. ESSCIRC 2012: 317-320 - [c15]Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 - [c14]Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 - [c13]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. ISSCC 2012: 232-234 - [c12]Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara:
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC 2012: 60-61 - 2011
- [j5]Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi:
Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. IEEE J. Solid State Circuits 46(9): 2180-2188 (2011) - [c11]Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano:
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. A-SSCC 2011: 165-168 - [c10]Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi:
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM. CICC 2011: 1-4 - [c9]Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano:
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC 2011: 1-4 - 2010
- [c8]Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. CICC 2010: 1-4 - [c7]Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara:
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC 2010: 354-357 - [c6]Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai:
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631
2000 – 2009
- 2008
- [c5]Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka:
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. ISSCC 2008: 276-277 - [c4]Tamio Ikehashi, Takayuki Miyazaki, Hiroaki Yamazaki, Atsushi Suzuki, Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima:
An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation. ISSCC 2008: 582-583 - 2006
- [c3]Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano:
A 65nm low-power embedded DRAM with extended data-retention sleep mode. ISSCC 2006: 567-576 - 2001
- [c2]Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano:
Interface socket design methodology to generate embedded DRAM macros. CICC 2001: 537-540 - 2000
- [j4]Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata:
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. IEEE J. Solid State Circuits 35(5): 705-712 (2000)
1990 – 1999
- 1999
- [j3]Shinji Miyano, Katsuhiko Sato, Kenji Numata:
Universal Test Interface for Embedded-DRAM Testing. IEEE Des. Test Comput. 16(1): 53-58 (1999) - 1998
- [j2]Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata:
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. IEEE J. Solid State Circuits 33(11): 1752-1757 (1998) - [c1]Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata:
A DRAM module generator with an expandable cell array scheme. CICC 1998: 287-290 - 1995
- [j1]Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea:
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. IEEE J. Solid State Circuits 30(11): 1281-1285 (1995)
Coauthor Index
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