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CN103681606A - 三维（3d）扇出封装机制 - Google Patents

三维（3d）扇出封装机制 Download PDF

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Publication number
CN103681606A
CN103681606A CN201210576132.XA CN201210576132A CN103681606A CN 103681606 A CN103681606 A CN 103681606A CN 201210576132 A CN201210576132 A CN 201210576132A CN 103681606 A CN103681606 A CN 103681606A
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China
Prior art keywords
interconnection structure
layer
semiconductor element
connector
interconnection
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CN201210576132.XA
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English (en)
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CN103681606B (zh
Inventor
林俊成
张进传
洪瑞斌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN103681606A publication Critical patent/CN103681606A/zh
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Abstract

本发明公开了三维(3D)扇出封装机制。形成半导体器件封装件的机制由于其相对简单的工艺流程而提供了低成本的制造工艺。通过形成具有能够将一个或多个管芯接合到封装结构下方的(一层或多层)再分配层的互连结构，大幅减少了整个封装件的翘曲。此外，在不使用模塑料的情况下形成互连结构，减少了颗粒污染。翘曲和颗粒污染的减少提高了成品率。而且，由于一个或多个管芯安装在封装结构和互连结构之间的间隔下方，所形成的半导体器件封装件具有低形状因数。

Description

三维(3D)扇出封装机制
技术领域
本发明涉及半导体封装，更具体而言，涉及三维(3D)扇出封装机制。 
背景技术
随着半导体技术的持续发展，半导体芯片/管芯变得越来越小。同时，更多的功能被集成到半导体管芯中。于是，半导体管芯具有封装到更小区域中的越来越多的输入/输出(I/O)焊盘。因此，半导体管芯的封装变得更加重要并且更具挑战性。 
发明内容
为了解决现有技术中存在的问题，根据本发明的一方面，提供了一种半导体封装件，包括：互连结构，其中所述互连结构包括再分配层(RDL)；半导体管芯，通过多个第一接合结构接合到所述互连结构，其中所述互连结构的RDL使得所述半导体管芯能够扇出连接；以及封装结构，通过多个第二接合结构接合到所述互连结构，其中所述半导体管芯置放置在所述封装结构和所述互连结构之间的间隔中。 
在所述的半导体封装件中，所述互连结构包括被一层或多层介电层围绕的导电结构。 
在所述的半导体封装件中，所述互连结构包括被一层或多层介电层围绕的导电结构，其中，所述一层或多层介电层由感光聚合物形成。 
在所述的半导体封装件中，所述互连结构的厚度等于或小于约30μm。 
在所述的半导体封装件中，被模塑层覆盖的所述互连结构和所述封装结构的总厚度介于约350μm至约1050μm的范围内。 
在所述的半导体封装件中，所述封装结构面向所述互连结构的第二表面的第一表面和所述第二表面之间的距离介于约100μm至约400μm的范围 内。 
在所述的半导体封装件中，多个连接元件与位于与所述半导体管芯和所述封装结构相对的表面上的互连结构接合。 
所述的半导体封装件还包括：邻近所述半导体管芯的另一半导体管芯，其中另一半导体管芯与所述互连结构接合并且放置在所述封装结构和所述互连结构之间的间隔中。 
在所述的半导体封装件中，所述封装结构包括两个或更多个半导体管芯。 
在所述的半导体封装件中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度。 
在所述的半导体封装件中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度，其中，所述第一连接件和所述第二连接件都包括阻挡层。 
在所述的半导体封装件中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度，其中，所述第一连接件和所述第二连接件都包括导电层。 
在所述的半导体封装件中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度，其中，所述第一宽度介于约20μm至约100μm的范围内。 
在所述的半导体封装件中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度，其中，所述第二宽度介于约100μm至约400μm的范围内。 
根据本发明的另一方面，提供了一种半导体封装件，包括：互连结构， 其中所述互连结构包括再分配层(RDL)，其中所述互连结构的厚度等于或小于约30μm；半导体管芯，通过多个第一接合结构接合到所述互连结构，其中所述互连结构的RDL使得所述半导体管芯能够扇出连接；以及封装结构，通过多个第二接合结构接合到所述互连结构，其中所述半导体管芯被放置在所述封装结构和所述互连件结构之间的间隔中。 
根据本发明的又一方面，提供了一种形成半导体封装件的方法，包括：提供其上设置有粘附层的载具；在所述粘附层上形成互连结构；将半导体管芯放置在所述互连结构的表面上；将封装结构放置在所述互连结构的表面上，其中所述半导体管芯安装在所述互连结构和所述封装结构之间的间隔中；以及实施回流以将所述封装结构接合到所述互连结构。 
在所述的方法中，所述回流还将所述半导体管芯接合到所述互连结构。 
所述的方法还包括：在将所述半导体管芯放置在所述互连结构的表面上之后以及在放置所述封装结构之前实施另一回流。 
在所述的方法中，所述互连结构包括再分配层(RDL)，并且所述互连层的RDL使得所述半导体管芯能够扇出连接。 
在所述的方法中，所述互连结构包括与所述半导体管芯接合的第一接触件和与所述封装结构接合的第二接触件，其中所述第一接触件小于所述第二接触件。 
附图说明
为了更充分地理解实施例及其优点，现在将参考结合附图所进行的以下描述，其中： 
图1A是根据一些实施例的封装件的截面图。 
图1B是根据一些实施例的封装件的一部分的截面图。 
图1C是根据一些实施例的与互连结构接合的两个管芯的截面图。 
图2A至图2G是根据一些实施例形成互连结构的连续工序流程的截面图。 
图3A至图3H是根据一些实施例形成封装件的连续工艺流程的截面图。 
具体实施方式
在下面详细论述本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例是示例性的，而不用于限制本发明的范围。 
图1A是根据一些实施例的封装件100的截面图。封装件100包括封装结构110和管芯120。封装结构110包括半导体管芯111和112。在一些实施例中，半导体管芯111和112中的每一个都包括如用于半导体集成电路制造的半导体衬底，并且可以在其中和/或在其上形成集成电路。半导体衬底指的是包含半导体材料的任何结构，包括但不限于体硅、半导体晶圆、绝缘体上硅(SOI)衬底或者硅锗衬底。还可以使用包括III族、IV族和V族元素的其他半导体材料。半导体衬底还可以包括多个隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或者硅的局部氧化(LOCOS)部件。隔离部件可以限定和隔离各种微电子元件。可以在半导体衬底中形成的各种微电子元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高电压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)；电阻器；二极管；电容器；电感器；熔丝；以及其他合适的元件。实施形成各种微电子元件的各种工艺包括沉积、蚀刻、注入、光刻、退火和/或其他合适的工艺。将微电子元件互连以形成集成电路器件，诸如逻辑器件、存储器器件(例如SRAM)、RF器件、输入/输出(I/O)器件、芯片上系统(SoC)器件、它们的组合以及其他合适的器件类型。 
半导体管芯111和112设置在衬底115上，在衬底115的表面上具有接触件116。如图1A所示，封装结构110的衬底115具有使衬底115的一个表面上的接触件116与衬底的相反表面上的接触件118连接的互连结构117。根据一些实施例，通过引线113和114分别将半导体管芯111和112电连接至接触件116。还可以通过其他方式使半导体管芯111和112连接至接触件116。衬底115中的互连结构117可以包括金属线和通孔。在一 些实施例中，互连结构117的通孔包括衬底通孔(TSV)或衬底穿孔(TSH)。位于衬底115的相反表面上的接触件118包括金属焊盘。在与互连结构130接合之前，接触件118还可以包括焊料层(未示出)。焊料层形成各个连接件119的一部分。将诸如焊料凸块或焊料球的连接件119接合到接触件118。在一些实施例中，连接件119的宽度(或直径)介于约100μm至约400μm的范围内。连接件119和接触件118形成接合结构124。 
如上所述，封装件100还包括管芯120。管芯120具有接触件122，其被一层或多层钝化层(未示出)围绕。在一些实施例中，接触件122包括金属焊盘123和在金属焊盘123上方形成的凸块。接触件122的凸块可以是焊料凸块和/或可以包括铜柱。接触件122的焊料凸块形成管芯120和互连结构130之间的接合结构125。在一些实施例中，接合结构125的宽度(或直径)介于约20μm至约100μm的范围内。根据一些实施例，连接件119大于接触件122。 
封装结构110的底面与互连结构130的顶面之间的距离在图1A中标记为H1。在一些实施例中，H1介于约100μm至约400μm的范围内。图1A还示出管芯120的厚度H2。H2小于H1，这容许管芯120利用封装结构110和互连结构130之间的间隔。 
如图1A所示，封装结构110和管芯120设置在互连结构130上方并且与互连结构130电连接。互连结构130包括一层或多层介电层，诸如介电层131和132。介电层131和132可以是软的(或者易弯曲的)以吸收在形成封装件100中所涉及的(一个或多个)接合工艺的应力。用于介电层131和132中的每一个的材料都可以选自可光定义的阻焊剂(photo-definable solder resists)；诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、模塑料的聚合物等。 
互连结构130的小接触件133与管芯120上的接触件122接合以形成接合结构125。而且互连结构130的大接触件134与封装结构110的连接件119接合以形成接合结构124。根据一些实施例，小接触件133小于大接触件134。而且，互连结构130的接触件135与连接元件140接合，连接元件140用于与诸如印刷电路板(PCB)的外部衬底或另一封装件形成 外部连接。连接元件140的高度在图1A中标记为H5。在一些实施例中，H5介于约100μm至约400μm的范围内。 
在一些实施例中，介电层131的厚度介于约3μm至约25μm的范围内。在一些实施例中，钝化层132的厚度介于约3μm至约15μm的范围内。互连结构130的总厚度在图1A中标记为H3。在一些实施例中，H3介于约6μm至约30μm的范围内。在一些实施例中，H3等于或小于约30μm。在一些实施例中，H3等于或小于约25μm。 
在图1A的实施例中，接触件135与金属线136连接，金属线136提供接合结构125、124和126之间的电连接。金属线136充当再分配层(RDL)并且使得管芯120能够扇出连接，该扇出连接允许超出管芯120的边缘(或边界)外的电连接。图1A的实施例仅包括一层金属层。然而，(一层或多层)RDL可以包括多层金属层，其可以通过通孔互连。在一些实施例中，接触件133和134包括凸块下金属(UBM)层211，其可以充当接触件133、134和接触件135之间的扩散阻挡层和能够电镀层(plating-enabling layer)。下面提供更多详细描述。 
在一些实施例中，接触件133的宽度介于约20μm至约100μm的范围内。在一些实施例中，接触件134的宽度介于约100μm至约400μm的范围内。在图1A的实施例中，接触件135包括导电层208和阻挡层205。下面提供对这些层及其形成方法的更多详细描述。 
在图1A的实施例中，封装结构110被模塑层(或模塑料)145覆盖。在一些实施例中，模塑层145包括环氧树脂、硅、二氧化硅填充剂和/或其他类型的聚合物。在图1A的实施例中，模塑层145还填充封装结构110和互连结构130之间的间隔。在一些实施例中，模塑层145还充当底部填充物(UF)并填充管芯120和互连结构130之间的间隔。在这种情况下，模塑层145是底部填充模塑(MUF)料，并且在将管芯120和封装结构110接合到互连结构130之后施加到互连结构130的表面上。在一些实施例中，在管芯120接合到互连结构130之后施加底部填充物144，如根据一些实施例的图1B所示。在施加底部填充物144之后，然后将封装结构110放置在互连结构130上方并且使其与互连结构130接合。位于互连结构130上 方的封装结构110的厚度在图1A中标记为H4。在一些实施例中，H4介于约350μm至约1000μm的范围内。封装件110和互连结构130的总厚度在图1A中标记为H6。在一些实施例，H6介于约350μm至1050μm的范围内。H6小于诸如介于约1000μm至约1500μm范围内的其他封装结构。因此，封装件100具有小的Z轴形状因数(或封装件100的总厚度)。 
在图1A的实施例中，将管芯120和封装结构110接合到互连结构130。在一些实施例中，在封装结构110下方具有多于一个的管芯。在图1C的实施例中，根据一些实施例，将两个管芯120’和120”接合到互连结构130’。在图1C的实施例中，将封装结构110’放置在管芯120’和120”的上方。 
图2A至图2G是根据一些实施例形成互连结构130的连续工艺流程的截面图。在图2A中，在载具201上形成粘附层202。根据一些实施例，载具201由玻璃制成。然而，其他材料也可以用于载具201。粘附层202设置(例如，层压)在载具201上。粘附层202可以由胶形成，或者可以是由箔形成的层压层。根据一些实施例，如图2B所示，在形成粘附层202之后，形成并且图案化钝化层203从而在粘附层202上形成接触开口204。在一些实施例中，钝化层203是介电材料。在一些实施例中，钝化层203是聚合物。在一些实施例中，钝化层203是感光聚合物并且可以在没有光刻胶层的情况下进行图案化。 
根据一些实施例，如图2C所示，在形成接触开口204之后，形成阻挡层205以覆盖载具201上的钝化层203的暴露表面。阻挡层205是导电层并且阻止为填充开口204而沉积的铜的扩散。在一些实施例中，阻挡层205由Ti制成。在一些实施例中，在阻挡层205上方形成铜晶种层(未示出)。在一些实施例中，通过物理汽相沉积(PVD)沉积阻挡层205和/或铜晶种层。在形成阻挡层205之后，然后在阻挡层上方形成光刻胶层206。在图2C中，光刻胶层206形成在阻挡层205上方。在一些实施例中，通过旋涂工艺(湿法工艺)形成光刻胶层206。在一些其他实施例中，光刻胶层206是干光刻胶层，其粘附于阻挡层205的表面，阻挡层205的表面可以被铜晶种层(未示出)覆盖。如图2C所示，然后图案化光刻胶层206以限定用于形成互连的开口207。 
在图2D中，根据一些实施例，在开口207和204中形成导电层208。在一些实施例中，导电层208是由铜或铜合金形成。根据一些实施例，导电层208包括诸如铝、镍、金、银、铂的(一种或多种)金属，上述金属的合金，或者它们的组合。在一些实施例中，通过镀法形成导电层208。根据一些实施例，通过诸如化学机械抛光(CMP)的去除工艺去除多余的导电层208或者导电层208太厚的区域。然后去除光刻胶层206。例如，如果光刻胶层206是干光刻胶膜，则其可以通过剥离去除。在一些实施例中，通过蚀刻工艺去除光刻胶层206。在去除光刻胶层206之后，暴露出阻挡层205被光刻胶层206覆盖的部分。然后如图2D所示，去除阻挡层205的暴露部分。在一些实施例中，通过蚀刻工艺去除阻挡层205的暴露部分。 
在图2E中，根据一些实施例，在钝化层203和导电层208的上方沉积另一钝化层209并对其进行图案化。在一些实施例中，钝化层209是介电材料。在一些实施例中，钝化层209是聚合物。在一些实施例中，钝化层209是感光聚合物并且可以在没有光刻胶层的情况下进行图案化。图案化工艺形成开口210。根据一些实施例，在形成开口210之后，在钝化层209的表面上沉积凸块下金属(UBM)层211。在一些实施例中，UBM层211包括扩散阻挡层和晶种层。在一些实施例中，扩散阻挡层还可以充当粘附层(或者胶合层)。扩散阻挡层可以由Ta、TaN、Ti、TiN或它们的组合形成。晶种层是由用于能够后续沉积导电层的材料形成。在一些实施例中，UBM层211包括由Ti形成的扩散阻挡层和由Cu形成的晶种层。在一些实施例中，通过物理汽相沉积(PVD)(或溅射)方法沉积诸如Ti层的扩散阻挡层和诸如Cu层的晶种层。 
根据一些实施例，如图2F所示，在形成UBM层211之后，在UBM层上方形成光刻胶层212。光刻胶层212可以是干光刻胶或湿光刻胶。图案化光刻胶层212以限定与开口210基本对准的开口213。在完成图案化工艺之后，形成用于填充开口210和213的导电层214。在一些实施例中，导电层214包括铜、铝、铜合金或其他流动性导电材料。在一些实施例中，导电层214由焊料形成。 
在一些实施例中，导电层214包括两个子层。一个子层是金属层，其由铜、铝、铜合金或具有低电阻率的其他导电材料形成。覆盖先前提到的子层的另一子层由焊料形成。在一些实施例中，根据一些实施例，如图2G所示，形成覆盖导电层214的保护层215。在一些实施例中，保护层215是可选的。之后，去除光刻胶层212，并且还去除由于光刻胶层的去除而暴露的UBM层211。在一些实施例中，通过镀法沉积导电层214。保护层215保护导电层214的表面不被氧化。在一些实施例中，保护层是由Ni或者一种有机表面保护(OSP)材料形成。在一些实施例中，UBM层211、导电层214以及可选的保护层215形成接触件133和134。图2G所示的接触件是接触件133或134。 
根据一些实施例，UBM层211和导电层214形成凸块结构。在一些实施例中，凸块结构是铜柱。形成铜柱的材料、结构以及形成方法的示例性细节记载在2010年7月29日提交的名称为“Mechanisms for Forming CopperPillar Bumps(形成铜柱凸块的机制)”(代理人案卷号TSMC2010-0205)的美国专利申请12/846,353中，将该申请的全部内容引入本文中。根据一些实施例，如图2G所示的形成在粘附层202上方的结构是互连结构130。 
图3A至图3H是根据一些实施例形成封装件100的连续工艺流程的截面图。在图3A的实施例中，在位于载具301上方的粘附层302上形成互连结构130。根据一些实施例的互连结构130的形成工艺和部件已在上文图2A至图2G中描述了。在一些实施例中，载具301与载具201类似，并且粘附层302与粘附层202类似。根据一些实施例，如图3B所示，在形成互连结构130之后，将管芯120放置在互连结构130上方。如图1A的更详细视图中所示，管芯120上的接触件122直接放置在互连结构130的接触件133上方并且与该接触件133接触。在一些实施例中，实施回流工艺以将接触件122接合到接触件133。在一些实施例中，在将接触件122和133接合到一起之后，施加底部填充物(UF)来填充管芯120和互连结构130的表面之间的间隔。图1B示出填充管芯120和互连结构130的表面之间的间隔的底部填充物144。如上所述，在一些实施例中未实施底部填充物的回流和施加，如图3B所示。 
根据一些实施例，如图3C所示，在将管芯120放置在互连结构130上之后，将封装结构110放置在互连结构130上。如图1A所述，将封装结构110上的连接件119直接放置在互连结构130上的接触件134的上方并且与该接触件134接触。如上所述，接触件134大于接触件133，因为封装结构110的连接件119大于管芯120上的接触件122。 
之后，根据一些实施例，如图3D所示，实施回流工艺以使接触件134和连接件119接合并且还使接触件133与接触件122接合。回流工艺将管芯120和封装结构110都接合到互连结构130。如上所述，在将管芯120放置在互连结构130上之后可以实施回流。在这种情况下，如图3D所描述，回流仅将接触件134接合到连接件119。 
在完成回流工艺之后，根据一些实施例，如图3E所示，施加模塑层145以覆盖封装结构110和管芯120。如上所述，在一些实施例中，模塑层145还充当底部填充物(UF)并且填充管芯120和互连结构130之间的间隔。然而，在一些其他实施例中，模塑层145还底部填充管芯120。 
在图3F中，根据一些实施例，去除载具301和粘附层302。如图2C所述，形成阻挡层205以内衬开口204。去除阻挡层205(例如Ti层)以暴露导电层208，根据一些实施例导电层208由铜制成。 
在图3G中，根据一些实施例，将诸如焊料球的连接元件140安装在互连结构130的表面上以与接触件135接合。接合工艺还包括回流。 
在将连接元件140接合到互连结构130之后，将图3G示出的封装结构固定到胶带，该胶带被固定到载具(未示出)。然后对图3G的带有固定后的封装结构的载具进行切割工艺以将封装件100分成单独的封装件。在切割工艺之后，从每一个封装件100分离胶带和载具(从载具除去胶带并除去接合)。图3H示出切割和除去胶带/除去接合工艺之后的封装件100。 
在管芯120、封装结构110、连接元件140和互连结构130之间形成的接合结构仅是一些实施例。具有不同形状和材料层的其他类型的接合结构也是可能的。 
由于相对简单的工艺流程，上面所述的形成半导体器件封装件的机制提供低成本的制造工艺。通过形成具有能够在封装结构下方接合一个或多 个管芯的(一层或多层)再分配层的互连结构，大幅减少了整个封装件的翘曲。此外，在不使用模塑料的情况下形成互连结构，减少了颗粒污染。翘曲和颗粒污染的减少提高了成品率。而且，由于一个或多个管芯安装在封装结构和互连结构之间的间隔下方，所形成的半导体器件封装件具有低形状因数。 
在一些实施例中，提供了一种半导体封装件。半导体封装件包括互连结构，而互连结构包括再分配层(RDL)。半导体封装件还包括通过多个第一接合结构接合到互连结构的半导体管芯，并且互连层的RDL使得半导体管芯能够扇出连接。半导体管芯进一步包括通过多个第二接合结构接合到互连结构的封装结构，并且半导体管芯被放置在封装结构和互连结构之间的间隔中。 
在一些其他实施例中，提供一种半导体封装件。半导体封装件包括互连结构，而互连结构包括再分配层(RDL)。互连结构的厚度等于或小于约30μm。半导体封装件还包括通过多个第一接合结构接合到互连结构的半导体管芯，并且互连层的RDL使得半导体管芯能够扇出连接。半导体封装件还包括通过多个第二接合结构接合到互连结构的封装结构，并且半导体管芯被放置在封装结构和互连结构之间的间隔中。 
在又一些其他实施例中，提供一种形成半导体封装件的方法。该方法包括：提供其上设置有粘附层的载具，并且在粘附层上形成互连结构。该方法还包括将半导体管芯放置在互连结构的表面上，并且将封装结构放置在互连结构的表面上。半导体管芯安装在互连结构和封装结构之间的间隔中。该方法还包括实施回流以将封装结构接合到互连结构。 
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的构思和范围的情况下，进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权 利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。 

Claims (10)

1.一种半导体封装件，包括：
互连结构，其中所述互连结构包括再分配层(RDL)；
半导体管芯，通过多个第一接合结构接合到所述互连结构，其中所述互连结构的RDL使得所述半导体管芯能够扇出连接；以及
封装结构，通过多个第二接合结构接合到所述互连结构，其中所述半导体管芯置放置在所述封装结构和所述互连结构之间的间隔中。
2.根据权利要求1所述的半导体封装件，其中，所述互连结构包括被一层或多层介电层围绕的导电结构。
3.根据权利要求2所述的半导体封装件，其中，所述一层或多层介电层由感光聚合物形成。
4.根据权利要求1所述的半导体封装件，其中，多个连接元件与位于与所述半导体管芯和所述封装结构相对的表面上的互连结构接合。
5.根据权利要求1所述的半导体封装件，还包括：
邻近所述半导体管芯的另一半导体管芯，其中另一半导体管芯与所述互连结构接合并且放置在所述封装结构和所述互连结构之间的间隔中。
6.根据权利要求1所述的半导体封装件，其中，所述互连结构包括用于与所述半导体管芯形成第一接合结构的第一连接件，以及用于与所述封装结构形成第二接合结构的第二连接件，其中所述第一连接件的第一宽度小于所述第二连接件的第二宽度。
7.根据权利要求6所述的半导体封装件，其中，所述第一连接件和所述第二连接件都包括阻挡层或者导电层。
8.一种半导体封装件，包括：
互连结构，其中所述互连结构包括再分配层(RDL)，其中所述互连结构的厚度等于或小于约30μm；
半导体管芯，通过多个第一接合结构接合到所述互连结构，其中所述互连结构的RDL使得所述半导体管芯能够扇出连接；以及
封装结构，通过多个第二接合结构接合到所述互连结构，其中所述半导体管芯被放置在所述封装结构和所述互连件结构之间的间隔中。
9.一种形成半导体封装件的方法，包括：
提供其上设置有粘附层的载具；
在所述粘附层上形成互连结构；
将半导体管芯放置在所述互连结构的表面上；
将封装结构放置在所述互连结构的表面上，其中所述半导体管芯安装在所述互连结构和所述封装结构之间的间隔中；以及
实施回流以将所述封装结构接合到所述互连结构。
10.根据权利要求9所述的方法，其中，所述互连结构包括再分配层(RDL)，并且所述互连层的RDL使得所述半导体管芯能够扇出连接。
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US9431367B2 (en) 2016-08-30
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KR20140030014A (ko) 2014-03-11
US8872326B2 (en) 2014-10-28
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US20160336280A1 (en) 2016-11-17
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US10276516B2 (en) 2019-04-30
US9960125B2 (en) 2018-05-01
US20180247900A1 (en) 2018-08-30
US20200294936A1 (en) 2020-09-17
US11362046B2 (en) 2022-06-14
US10672723B2 (en) 2020-06-02
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US20190252329A1 (en) 2019-08-15
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TW201409641A (zh) 2014-03-01

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