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ITC 2010: Austin, TX, USA
- Ron Press, Erik H. Volkerink:
2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7206-2
Session 1: Building low cost ate in the GHz era
- Jun Kohno, Tatsuro Akiyama, Dai Kato, Makoto Imamura:
A high linearity compact timing vernier for CMOS timing generator. 1-8 - Timothy Daniel Lyons:
Complete testing of receiver jitter tolerance. 9-18 - Raphael Robertazzi, Louis Medina, Ernesto Shiling, Garry Moore, Ronald Geiger, Jiun-Hsin Liao, John Williamson:
New tools and methodology for advanced parametric and defect structure test. 19-28 - Sadok Aouini, Kun Chuai, Gordon W. Roberts:
A low-cost ATE phase signal generation technique for test applications. 29-38
Session 2: Microprocessor test
- Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen:
The scan-DFT features of AMD's next-generation microprocessor core. 39-48 - James Crafts, David Bogdan, Dennis Conti, Donato O. Forlenza, Orazio P. Forlenza, William V. Huott, Mary P. Kusko, Edward Seymour, Timothy Taylor, Brian Walsh:
Testing the IBM Power 7™ 4 GHz eight core microprocessor. 49-58 - Minki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay:
Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration. 59-68 - David Iverson, Dan Dickinson, John Masson, Christina Newman-LaBounty, Daniel Simmons, William Tanona:
Redundant core testing on the cell BE microprocessor. 68-73
Session 3: DFT advances
- Stephen K. Sunter, Matthias Tilmann:
BIST of I/O circuit parameters via standard boundary scan. 74-83 - Narendra Devta-Prasanna, Arun Gunda:
Clock Gate Test Points. 84-93 - Kun Young Chung, Sandeep K. Gupta:
Design and test of latch-based circuits to maximize performance, yield, and delay test quality. 94-103 - Fan Yang, Sreejit Chakravarty:
Testing of latch based embedded arrays using scan tests. 104-113
Session 4: Various ATPG techniques
- Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab:
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. 114-123 - V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar:
Towards effective and compression-friendly test of memory interface logic. 124-133 - Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli:
Test cycle power optimization for scan-based designs. 134-143
Session 5: Post-silicon validation
- Ho Fai Ko, Nicola Nicolici:
Automated trace signals selection using the RTL descriptions. 144-153 - Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner
, Subhasish Mitra:
QED: Quick Error Detection tests for effective post-silicon validation. 154-163 - Po-Hsien Chang, Li-C. Wang
A kernel-based approach for functional test program generation. 164-173
Session 6: 3-D Test
- Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu
Modeling TSV open defects in 3D-stacked DRAM. 174-182 - Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen
On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. 183-192 - Brandon Noia, Krishnendu Chakrabarty
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. 193-201
Session 7: Memory online test and fault tolerance
- Saeed Shamshiri, Kwang-Ting Cheng
Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. 202-211 - Rudrajit Datta, Nur A. Touba:
Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. 212-218 - Rance Rodrigues, Sandip Kundu, Omer Khan:
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. 219-228
Session 8: RF test techniques
- Koji Asami, Toshiaki Kurihara, Yushi Inada:
Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers. 229-236 - Devin Morris, William R. Eisenstadt
Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude. 237-244 - Nathan Kupp, He Huang, Petros Drineas
Post-production performance calibration in analog/RF devices. 245-254
Session 9: Scan compression
- Peter Wohl, John A. Waicukauski, T. Finklea:
Increasing PRPG-based compression by delayed justification. 255-264 - Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
Dynamic channel allocation for higher EDT compression in SoC designs. 265-274 - Ozgur Sinanoglu
Predictive analysis for projecting test compression levels. 275-284
Session 10: Detecting and understanding defects
- Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger:
Defect-oriented cell-internal testing. 285-294 - S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu:
Modeling the impact of process variation on resistive bridge defects. 295-304 - Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton:
Automatic classification of bridge defects. 305-314
Session 11: I love RF
- Masayuki Kimishima, S. Mizuno, T. Seki, H. Takeuti, Haruki Nagami, Hideki Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi:
A high density small size RF test module for high throughput multiple resource testing. 315-324 - Sukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzlar, Richard Antley, Craig Force, Falah Mohammed:
RADPro: Automatic RF analyzer and diagnostic program generation tool. 325-333 - Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi:
Timing skew compensation technique using digital filter with novel linear phase condition. 334-342
Session 12: Parallel TG and fault simulation and diagnostic TG
- Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. 343-352 - X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath:
Highly efficient parallel ATPG based on shared memory. 353-359 - Yu Zhang, Vishwani D. Agrawal:
A diagnostic test generation system. 360-368
Session 13: DFM and yield-learning via design and data analysis
- Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang:
Mask versus Schematic - an enhanced design-verification flow for first silicon success. 369-377 - Wing Chiu Tam, Osei Poku, Ronald D. Blanton:
Systematic defect identification through layout snippet clustering. 378-387 - Rao Desineni, Leah Pastel, Maroun Kassab, Robert Redburn:
Hard to find, easy to find systematics; just find them. 388-397
Session 14: DFT for HF ICS
- Deepa Mannath, Dallas Webster, Victor Montaño-Martinez, David Cohen, Shai Kush, Ganesan Thiagarajan, Adesh Sontakke:
Structural approach for built-in tests in RF devices. 398-404 - Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran:
Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. 405-409 - Rakesh Kinger, Swetha Narasimhawsamy, Stephen K. Sunter:
Experiences with parametric BIST for production testing PLLs with picosecond precision. 410-418 - Tomohiro Kawachi, Koichi Irie:
ADC linearity testing method with single analog monitoring port. 419-426
Session 15: Memory testing
- Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang:
Fault models and test methods for subthreshold SRAMs. 427-436 - Sandra Irobi, Zaid Al-Ars, Said Hamdioui:
Detecting memory faults in the presence of bit line coupling in SRAM devices. 437-446 - Paolo Bernardi
A programmable BIST for DRAM testing and diagnosis. 447-456 - Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar
Rapid FPGA delay characterization using clock synthesis and sparse sampling. 457-466
Session 16: Advanced topics in board test
- Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird:
Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing. 467-476 - Luca Amati, Cristiana Bolchini
Improving fault diagnosis accuracy by automatic test set modification. 477-484 - Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty
Board-level fault diagnosis using an error-flow dictionary. 485-494 - Rosa D. Reinosa, Aileen Allen, Elizabeth Benedetto, Alan Mcallister:
Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test. 495-505
Session 17: Faster to market, faster to test: ATE SW advances
- Anke Drappa, Peter Huber, Jon Vollmar:
Automated test program generation for automotive devices. 1-10 - Jim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas:
STIL P1450.4: A standard for test flow specification. 506-515 - Bethany Van Wagenen, Edward Seng:
Concurrent test planning. 516-525 - Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash:
Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. 526-535
Session 18: Mircoprocessor test - At speed learning
- Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche:
Path coverage based functional test generation for processor marginality validation. 544-552 - Janine Chen, Brendon Bolin, Li-C. Wang
Mining AC delay measurements for understanding speed-limiting paths. 553-562
Session 19: New issues and enhancements to IEEE 1149.1
- C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill:
Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins. 563-570 - Kenneth P. Parker:
Surviving state disruptions caused by test: The "Lobotomy Problem". 571-578 - Lee Whetsel:
Commanded Test Access Port operations. 579-588
Session 20: Ate for when just 1 and 0 is not enough
- Carl Karandjeff, Chris Hannaford:
Precision audio nulling instrumentation achieves near -140dB measurements in a production environment. 589-598 - Suri Basharapandiyan, Yi Cai:
Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs. 599-605 - Ki-Jae Song, Hunkyo Seo, Sang-hyun Ko:
Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages. 606-614
Session 21: RTL, high-level test and timing emulation
- Marie Engelene J. Obien
Constrained ATPG for functional RTL circuits using F-Scan. 615-624 - Alodeep Sanyal, Krishnendu Chakrabarty
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. 625-634 - Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam:
A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. 635-644
Session 22: Charaterize! Variability, defects, bio-fluidics
- Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic:
Leveraging existing power control circuits and power delivery architecture for variability measurement. 645-653 - Qais Al-Gayem, Hongyuan Liu, Andrew Richardson
An on-line monitoring technique for electrode degradation in bio-fluidic microsystems. 654-663 - Xiaochun Yu, Ronald D. Blanton:
Estimating defect-type distributions through volume diagnosis and defect behavior attribution. 664-673
Session 23: New ways to test analog
- Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
Adaptive test flow for mixed-signal/RF circuits using learned information from device under test. 674-683 - Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris
Analog neural network design for RF built-in self-test. 684-693 - Jingbo Duan, Le Jin, Degang Chen:
A new method for estimating spectral performance of ADC from INL. 694-703 - Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer:
Low power compression of incompatible test cubes. 704-713 - Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. 714-723 - Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise:
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. 724-733
Session 25: Soft-error tolerance and multicore testing
- Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González
MT-SBST: Self-test optimization in multithreaded multicore architectures. 734-743 - Warin Sootkaneung
On techniques for handling soft errors in digital circuits. 744-752 - Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori:
Soft error reliability aware placement and routing for FPGAs. 753-761
Panel Discussions
- Al Czamara:
AXIe®: Open architecture test system standard. 801 - Kenneth Spargo:
AXIe® 2.0 and MVP-C: Open ATE software standards. 802 - Ankush Srivastava, Ajay Prajapati, Vinay Soni:
A novel approach to improve test coverage of BSR cells. 803 - Nabeeh Kandalaft, Iftekhar Ibne Basith, Rashid Rashidzadeh:
A MEMS based device interface board. 804 - Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? 805 - Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda
A tester architecture suitable for MEMS calibration and testing. 806 - Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng:
The AB-filling methodology for power-aware at-speed scan testing. 807 - Michele Portolan
Scan chain securization though Open-Circuit Deadlocks. 808 - Sara Karamati, Zainalabedin Navabi:
Using context based methods for test data compression. 809 - Jean-Marc Gallière, Paolo Rech
A roaming memory test bench for detecting particle induced SEUs. 810 - Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson:
Detecting and diagnosing open defects. 811 - Sarveswara Tammali, Vishal Khatri, Gowrysankar Shanmugam, Mark Terry:
DFM aware bridge pair extraction for manufacturing test development. 812 - Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe:
Methodology for early and accurate test power estimation at RTL. 813 - Kelly Lee:
A practical scan re-use scheme for system test. 814 - Shujun Deng, Kwang-Ting Cheng
Mutation-based diagnostic test generation for hardware design error diagnosis. 815 - Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
On generation of a universal path candidate set containing testable long paths. 816 - Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
System reliability evaluation using concurrent multi-level simulation of structural faults. 817 - Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen:
Case study of scan chain diagnosis and PFA on a low yield wafer. 818 - Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday:
Vendor-agnostic native compression engine. 819 - D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. 820 - Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz:
Multiple fault activation cycle tests for transistor stuck-open faults. 821
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