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Mango Chia-Tso Chao
Mango C.-T. Chao
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2020 – today
- 2024
- [c59]Liang-Ting Chen, Hung-Ru Kuo, Yih-Lang Li, Mango C.-T. Chao:
Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search. DAC 2024: 218:1-218:6 - [c58]Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen
, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. VTS 2024: 1-7 - 2023
- [j19]Chia-Heng Yen
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4282-4295 (2023) - [j18]Wei-Tse Hung, Yu-Guang Chen
DRC Violation Prediction After Global Route Through Convolutional Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1425-1438 (2023) - [c57]Jhen-Gang Lin
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. ACM Great Lakes Symposium on VLSI 2023: 313-319 - [c56]Ching-Min Liu, Chia-Heng Yen
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. ITC 2023: 357-366 - [c55]Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Outlier Detection for Analog Tests Using Deep Learning Techniques. VTS 2023: 1-7 - [c54]Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao:
Test Generation for Defect-Based Faults of Scan Flip-Flops. VTS 2023: 1-7 - 2022
- [j17]Yu-Teng Nien
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5057-5070 (2022) - [j16]Shuo-Wen Chang, Yu-Teng Nien
Test Methodology for Defect-Based Bridge Faults. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 975-988 (2022) - [c53]Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao:
Improving Cell-Aware Test for Intra-Cell Short Defects. DATE 2022: 436-441 - [c52]Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao:
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ISPD 2022: 107-115 - [c51]Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang:
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. ISQED 2022: 1-6 - [c50]Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao:
Rule Generation for Classifying SLT Failed Parts. VTS 2022: 1-7 - 2021
- [c49]Cheng-Hao Yang, Chia-Heng Yen
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS 2021: 1-7 - 2020
- [c48]Wen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, Mango C.-T. Chao:
Power Distribution Network Generation for Optimizing IR-Drop Aware Timing. ICCAD 2020: 146:1-146:9 - [c47]Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao:
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. ISPD 2020: 57-64 - [c46]Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao:
Test Methodology for Defect-based Bridge Faults. ITC-Asia 2020: 106-111 - [c45]Chun-Teng Chen, Chia-Heng Yen
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS 2020: 1-6
2010 – 2019
- 2019
- [c44]Yu-Teng Nien
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC 2019: 1-10 - [c43]Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang:
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT 2019: 1-4 - [c42]Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee:
Layout-Based Dual-Cell-Aware Tests. VTS 2019: 1-6 - 2018
- [j15]Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2139-2151 (2018) - [c41]Keng-Wei Chang, Chun-Yang Huang, Szu-Pang Mu, Jian-Min Huang, Shi-Hao Chen, Mango C.-T. Chao:
DVFS Binning Using Machine-Learning Techniques. ITC-Asia 2018: 31-36 - 2017
- [j14]Wen-Hsiang Chang
Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1237-1250 (2017) - [c40]Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. ASP-DAC 2017: 426-431 - [c39]Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien
Methodology of generating dual-cell-aware tests. VTS 2017: 1-6 - [c38]Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao:
Fast WAT test structure for measuring Vt variance based on latch-based comparators. VTS 2017: 1-6 - 2016
- [j13]Shu-Yung Bin, Shih-Feng Lin, Ya Ching Cheng, Wen-Rong Liau, Alex Hou, Mango C.-T. Chao:
Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 625-637 (2016) - [j12]Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang:
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1675-1687 (2016) - [c37]Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai:
Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax. ICCAD 2016: 116 - [c36]Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango Chia-Tso Chao, Cheng-Hong Tsai, Yen-Chih Chiu:
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique. ISPD 2016: 145-152 - [c35]Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. VTS 2016: 1-6 - 2015
- [c34]Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao:
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. ITC 2015: 1-10 - [c33]Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao:
Statistical techniques for predicting system-level failure using stress-test data. VTS 2015: 1-6 - [c32]Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao:
Random pattern generation for post-silicon validation of DDR3 SDRAM. VTS 2015: 1-6 - 2014
- [j11]Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen:
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1069-1081 (2014) - [j10]Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee:
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1138-1149 (2014) - [j9]Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu:
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1294-1307 (2014) - [c31]Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li:
Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. VLSI-DAT 2014: 1-4 - [c30]Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang:
Testing methods for a write-assist disturbance-free dual-port SRAM. VTS 2014: 1-6 - 2013
- [j8]Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Chin-Yuan Huang, Mango Chia-Tso Chao, Rei-Fu Huang:
Fault Models and Test Methods for Subthreshold SRAMs. IEEE Trans. Computers 62(3): 468-481 (2013) - [j7]Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao:
Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 413-423 (2013) - [c29]Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao:
Testing retention flip-flops in power-gated designs. VTS 2013: 1-6 - [c28]Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu:
Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs. VTS 2013: 1-6 - [c27]Chen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao:
Testing of a low-VMIN data-aware dynamic-supply 8T SRAM. VTS 2013: 1-6 - 2012
- [j6]Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin:
Testing Methodology of Embedded DRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1715-1728 (2012) - [c26]Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao:
An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. ASP-DAC 2012: 59-65 - [c25]Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin:
Alternate hammering test for application-specific DRAMs and an industrial case study. DAC 2012: 1012-1017 - [c24]Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang:
Testing strategies for a 9T sub-threshold SRAM. ITC 2012: 1-10 - 2011
- [j5]Chen-Wei Lin, Mango C.-T. Chao, Yen-Shih Huang:
A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 939-952 (2011) - [j4]Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang:
A Novel Test Flow for One-Time-Programming Applications of NROM Technology. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2170-2183 (2011) - [c23]Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao:
Detecting stability faults in sub-threshold SRAMs. ICCAD 2011: 28-33 - [c22]Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen:
Design-for-debug layout adjustment for FIB probing and circuit editing. ITC 2011: 1-9 - 2010
- [j3]Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang:
A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 240-245 (2010) - [j2]Yu-Ze Wu, Mango Chia-Tso Chao:
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes. ACM Trans. Design Autom. Electr. Syst. 16(1): 10:1-10:29 (2010) - [c21]Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai:
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ICCAD 2010: 155-161 - [c20]Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin:
Mathematical yield estimation for two-dimensional-redundancy memory arrays. ICCAD 2010: 235-240 - [c19]Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang:
Mask versus Schematic - an enhanced design-verification flow for first silicon success. ITC 2010: 369-377 - [c18]Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang:
Fault models and test methods for subthreshold SRAMs. ITC 2010: 427-436 - [c17]Szu-Pang Mu, Mango Chia-Tso Chao:
Theoretical analysis for low-power test decompression using test-slice duplication. VTS 2010: 147-152
2000 – 2009
- 2009
- [c16]Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin:
Fault models for embedded-DRAM macros. DAC 2009: 714-719 - [c15]Tsun-Ming Tseng
Power-switch routing for coarse-grain MTCMOS technologies. ICCAD 2009: 39-46 - [c14]Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang:
A metal-only-ECO solver for input-slew and output-loading violations. ISPD 2009: 191-198 - [c13]Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao:
A novel test flow for one-time-programming applications of NROM technology. ITC 2009: 1-9 - [c12]Tseng-Chin Luo, Mango Chia-Tso Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young:
A novel array-based test methodology for local process variation monitoring. ITC 2009: 1-9 - [c11]Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu:
Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS 2009: 123-128 - 2008
- [c10]Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen:
Testing Methodology of Embedded DRAMs. ITC 2008: 1-9 - [c9]Yu-Ze Wu, Mango Chia-Tso Chao:
Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. VTS 2008: 147-154 - 2007
- [c8]Mango Chia-Tso Chao, Kwang-Ting Cheng
A hybrid scheme for compacting test responses with unknown values. ICCAD 2007: 513-519 - 2006
- [c7]Mango Chia-Tso Chao, Kwang-Ting Cheng
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC 2006: 1083-1088 - [c6]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
Coverage loss by using space compactors in presence of unknown values. DATE 2006: 1053-1054 - 2005
- [c5]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD 2005: 80-87 - [c4]Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD 2005: 147-152 - 2004
- [j1]Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integr. 38(2): 245-265 (2004) - [c3]Mango Chia-Tso Chao, Li-C. Wang
Pattern Selection for Testing of Deep Sub-Micron Timing Defects. DATE 2004: 160 - 2001
- [c2]Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang:
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD 2001: 335-347
1990 – 1999
- 1999
- [c1]Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD 1999: 364-369
Coauthor Index
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