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Krishna Chakravadhanula
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2020 – today
- 2022
- [c15]Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran:
PPA Optimization of Test Points in Automotive Designs. ITC 2022: 204-212
2010 – 2019
- 2019
- [c14]Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula:
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ITC 2019: 1-6 - 2018
- [c13]Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula:
Improving Diagnosis Resolution and Performance at High Compression Ratios. ITC 2018: 1-8 - 2017
- [c12]Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox:
Advancing test compression to the physical dimension. ITC 2017: 1-10 - [c11]Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula:
High throughput multiple device diagnosis system. ITC 2017: 1-10 - 2015
- [c10]Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling:
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW 2015: 43-48 - 2014
- [c9]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen:
Efficient testing of hierarchical core-based SOCs. ITC 2014: 1-10 - [c8]Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula:
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSID 2014: 5-6 - 2013
- [c7]Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj:
SmartScan - Hierarchical test compression for pin-limited low power designs. ITC 2013: 1-9 - 2010
- [c6]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise:
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733
2000 – 2009
- 2009
- [j1]Krishna Chakravadhanula, Vivek Chickermane:
Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Des. Test Comput. 26(3): 6-15 (2009) - [c5]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman:
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium 2009: 295-300 - [c4]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang:
Capture power reduction using clock gating aware test generation. ITC 2009: 1-9 - 2008
- [c3]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor:
Test Generation for State Retention Logic. ATS 2008: 237-242 - [c2]Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula:
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC 2008: 1-10 - 2007
- [c1]Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane:
Low Power Reduced Pin Count Test Methodology. ATS 2007: 251-258
Coauthor Index
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