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Suriyaprakash Natarajan
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2020 – today
- 2024
- [j8]Shamik Kundu
, Suvadeep Banerjee
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 217-229 (2024) - [c45]Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu:
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. DAC 2024: 206:1-206:6 - [c44]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Generating Storage-Aware Test Sets Targeting Several Fault Models. ISVLSI 2024: 15-20 - [c43]Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev:
Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. VTS 2024: 1-7 - [i1]Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu:
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. CoRR abs/2404.01632 (2024) - 2023
- [j7]Shamik Kundu
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators. IEEE Des. Test 40(2): 90-99 (2023) - [j6]Shamik Kundu
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators. IEEE Trans. Computers 72(8): 2194-2208 (2023) - [j5]Ayush Arunachalam
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1085-1098 (2023) - [c42]Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu:
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. ITC 2023: 266-275 - 2022
- [c41]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS 2022: 120-125 - [c40]Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris:
A defect tolerance framework for improving yield. DAC 2022: 847-852 - [c39]Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee:
DEFCON: Defect Acceleration through Content Optimization. ITC 2022: 298-304 - 2021
- [j4]Shamik Kundu
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 485-498 (2021) - [c38]Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators. ISQED 2021: 457-462 - [c37]Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee:
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS 2021: 1-7 - 2020
- [c36]Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee:
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC 2020: 1-10 - [c35]Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang:
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. ITC 2020: 1-10 - [c34]Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen:
Automated Design For Yield Through Defect Tolerance. VTS 2020: 1-6
2010 – 2019
- 2019
- [c33]Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee:
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology. ITC 2019: 1-10 - 2017
- [j3]Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
A novel test compression algorithm for analog circuits to decrease production costs. Integr. 58: 538-548 (2017) - [c32]Suriya Natarajan, Abhijit Sathaye:
Innovative practices session 4C data analytics in test. VTS 2017: 1 - [c31]Jeyavijayan (JV) Rajendran, Peilin Song, Suriya Natarajan:
Innovative practices session 3C hardware security. VTS 2017: 1 - 2016
- [j2]Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury:
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 319-329 (2016) - [c30]Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC 2016: 539-544 - [c29]Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary:
Fault simulation for analog test coverage. ITC 2016: 1-7 - [c28]Suvadeep Banerjee
Infant mortality tests for analog and mixed-signal circuits. VTS 2016: 1-6 - [c27]Suriyaprakash Natarajan, Li-C. Wang:
Session 4B - Panel data analytics in semiconductor manufacturing. VTS 2016: 1 - 2015
- [c26]Ashwin Chintaluri, Abhinav Parihar
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. ATS 2015: 187-192 - [c25]Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan:
Fast eye diagram analysis for high-speed CMOS circuits. DATE 2015: 1377-1382 - [c24]Chong Li, Suriyaprakash Natarajan, Chuanjin Richard Shi:
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS 2015: 478-481 - [c23]Sreekumar V. Kodakara, Suriya Natarajan:
Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts? VTS 2015: 1 - [c22]Suriya Natarajan:
Innovative practices session 7C: Mixed signal test and debug. VTS 2015: 1 - 2014
- [c21]Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. ITC 2014: 1-10 - [c20]Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang:
Innovative practices session 4C: Disruptive solutions in the non-digital world. VTS 2014: 1 - [c19]Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran:
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS 2014: 1 - 2013
- [c18]Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti:
Scalable and efficient analog parametric fault identification. ICCAD 2013: 387-392 - [c17]Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue:
Framework for analog test coverage. ISQED 2013: 468-475 - [c16]Helia Naeimi, Suriya Natarajan, Kushagra Vaid, Prabhakar Kudva, Mahesh Natu:
Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity. VTS 2013: 1 - [c15]Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas:
Special session 12B: Panel post-silicon validation & test in huge variance era. VTS 2013: 1 - 2011
- [c14]Suriyaprakash Natarajan, Arani Sinha:
The buck stops with wafer test: Dream or reality? VTS 2011: 111 - [c13]Arani Sinha, Suriyaprakash Natarajan:
The bang for the buck with resiliency: Yield or field? VTS 2011: 152 - 2010
- [c12]Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche:
Path coverage based functional test generation for processor marginality validation. ITC 2010: 544-552 - [c11]Suriyaprakash Natarajan:
Innovative practices session 9C: Implications of power delivery network for validation and testing. VTS 2010: 282
2000 – 2009
- 2008
- [j1]Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani:
Case Study on Speed Failure Causes in a Microprocessor. IEEE Des. Test Comput. 25(3): 224-230 (2008) - [c10]Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan:
On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI 2008: 279-284 - [c9]I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9 - 2007
- [c8]Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil:
The Region-Exhaustive Fault Model. ATS 2007: 13-18 - 2006
- [c7]Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz:
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT 2006: 59-70 - [c6]Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23 - 2005
- [c5]Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium 2005: 194-201 - 2002
- [c4]Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374 - 2001
- [c3]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test of domino logic circuits. ITC 2001: 367-376
1990 – 1999
- 1999
- [c2]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test. ITC 1999: 171-180 - 1998
- [c1]Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta:
Process Variations and their Impact on Circuit Operation. DFT 1998: 73-
Coauthor Index
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