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Omer Khan
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- affiliation: University of Connecticut, USA
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2020 – today
- 2024
- [c60]Hongwu Peng
, Xi Xie
MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training. ASPLOS (2) 2024: 683-698 - [c59]Zachary DiMeglio, Jenna Bustami, Deniz Gurevin, Chenglu Jin, Marten van Dijk, Omer Khan:
Masked Memory Primitive for Key Insulated Schemes. HOST 2024: 293-303 - [c58]Deniz Gurevin, Mohsin Shan, Shaoyi Huang, Md Amit Hasan, Caiwen Ding, Omer Khan:
PruneGNN: Algorithm-Architecture Pruning Framework for Graph Neural Network Acceleration. HPCA 2024: 108-123 - [d2]Hongwu Peng
ASPLOS 2024 Artifact for "MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training". Version 1. Zenodo, 2024 [all versions] - [d1]Hongwu Peng
ASPLOS 2024 Artifact for "MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training". Version 2. Zenodo, 2024 [all versions] - 2023
- [j28]Usman Ali
Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware. ACM J. Emerg. Technol. Comput. Syst. 19(3): 21:1-21:23 (2023) - [j27]Abdul Rasheed Sahni
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes. ACM Trans. Archit. Code Optim. 20(3): 32:1-32:24 (2023) - [c57]Xi Xie, Hongwu Peng, Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding:
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks. ICCAD 2023: 1-9 - [c56]Mohsin Shan, Deniz Gurevin, Jared Nye, Caiwen Ding, Omer Khan:
MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration. ISPASS 2023: 145-156 - [i12]Xi Xie, Hongwu Peng, Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding:
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks. CoRR abs/2308.11825 (2023) - [i11]Hongwu Peng, Xi Xie, Kaustubh Shivdikar, Md Amit Hasan, Jiahui Zhao, Shaoyi Huang, Omer Khan, David R. Kaeli, Caiwen Ding:
MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training. CoRR abs/2312.08656 (2023) - [i10]Usman Ali, Hamza Omar, Chujiao Ma, Vaibhav Garg, Omer Khan:
Hardware Root-of-Trust implementations in Trusted Execution Environments. IACR Cryptol. ePrint Arch. 2023: 251 (2023) - 2022
- [j26]Jared Nye
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors. IEEE Comput. Archit. Lett. 21(2): 129-132 (2022) - [j25]Akif Rehman
A performance predictor for implementation selection of parallelized static and temporal graph algorithms. Concurr. Comput. Pract. Exp. 34(2) (2022) - [c55]Mohsin Shan, Omer Khan:
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores. HPCA 2022: 528-542 - [c54]Usman Ali
MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores. ICCD 2022: 97-104 - [c53]Deniz Gurevin, Mohsin Shan, Tong Geng, Weiwen Jiang, Caiwen Ding, Omer Khan:
Towards Real-Time Temporal Graph Learning. ICCD 2022: 263-271 - [c52]Hongwu Peng
Towards Sparsification of Graph Neural Networks. ICCD 2022: 272-279 - [c51]Yixuan Luo, Payman Behnam, Kiran Thorat, Zhuo Liu, Hongwu Peng
CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM. ICCD 2022: 280-289 - [c50]Zhirui Hu, Jinyang Li, Zhenyu Pan
On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond. ICCD 2022: 290-297 - [c49]Usman Ali
Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware. ISQED 2022: 1-6 - [c48]Usman Ali
Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores. SEED 2022: 190-201 - [i9]Deniz Gurevin, Chenglu Jin, Phuong Ha Nguyen, Omer Khan, Marten van Dijk:
Secure Remote Attestation with Strong Key Insulation Guarantees. CoRR abs/2201.01834 (2022) - [i8]Hongwu Peng
Towards Sparsification of Graph Neural Networks. CoRR abs/2209.04766 (2022) - [i7]Deniz Gurevin, Mohsin Shan, Tong Geng, Weiwen Jiang, Caiwen Ding, Omer Khan:
Towards Real-Time Temporal Graph Learning. CoRR abs/2210.04114 (2022) - 2021
- [j24]Mohsin Shan, Omer Khan
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores. IEEE Comput. Archit. Lett. 20(1): 17-21 (2021) - [j23]Hamza Omar, Omer Khan:
PRISM: Strong Hardware Isolation-based Soft-Error Resilient Multicore Architecture with High Performance and Availability at Low Hardware Overheads. ACM Trans. Archit. Code Optim. 18(3): 31:1-31:25 (2021) - [c47]Usman Ali
ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor. HOST 2021: 192-202 - [c46]Deniz Gurevin, Chris J. Michael, Omer Khan:
An Efficient Algorithm for the Construction of Dynamically Updating Trajectory Networks. HPEC 2021: 1-7 - [c45]Salman Abdul Khaliq, Usman Ali
Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems. HPEC 2021: 1-7 - [c44]Omer Khan, Ravi Soundararajan:
Message from the General Chairs. IISWC 2021: viii - [c43]Brandon D'Agostino
Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors. SEED 2021: 203-209 - [i6]Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen:
Autonomous Secure Remote Attestation even when all Used and to be Used Digital Keys Leak. IACR Cryptol. ePrint Arch. 2021: 602 (2021) - [i5]Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen:
Bilinear Map Based One-Time Signature Scheme with Secret Key Exposure. IACR Cryptol. ePrint Arch. 2021: 925 (2021) - 2020
- [j22]Masab Ahmad, Halit Dogan, José A. Joao, Omer Khan:
In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores. IEEE Micro 40(1): 83-92 (2020) - [j21]Hamza Omar
OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks. IEEE Trans. Computers 69(11): 1558-1570 (2020) - [c42]Hamza Omar, Omer Khan:
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications. HPCA 2020: 111-122 - [c41]Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan:
Accelerating relax-ordered task-parallel workloads using multi-level dependency checking. ICS 2020: 36:1-36:11 - [c40]Akif Rehman, Masab Ahmad, Omer Khan:
Exploring accelerator and parallel graph algorithmic choices for temporal graphs. PMAM@PPoPP 2020: 7:1-7:10
2010 – 2019
- 2019
- [j20]Halit Dogan, Masab Ahmad, Brian Kahne, Omer Khan:
Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale. ACM Trans. Archit. Code Optim. 16(1): 4:1-4:27 (2019) - [j19]Syed Kamran Haider
Advancing the State-of-the-Art in Hardware Trojans Detection. IEEE Trans. Dependable Secur. Comput. 16(1): 18-32 (2019) - [j18]Ozgur Sinanoglu
Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. 7(2): 242-243 (2019) - [c39]Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan:
POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms. PACT 2019: 495-496 - [c38]Masab Ahmad, Halit Dogan, Christopher J. Michael, Omer Khan:
HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators. ISPASS 2019: 268-281 - [i4]Hamza Omar, Omer Khan:
IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks. CoRR abs/1904.12729 (2019) - 2018
- [j17]Hamza Omar, Halit Dogan, Brian Kahne, Omer Khan
Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications. IEEE Comput. Archit. Lett. 17(2): 230-234 (2018) - [j16]Hamza Omar, Qingchuan Shi, Masab Ahmad, Halit Dogan, Omer Khan:
Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency. ACM Trans. Embed. Comput. Syst. 17(4): 76:1-76:27 (2018) - [j15]Maria K. Michael
Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology. IEEE Trans. Emerg. Top. Comput. 6(4): 447-449 (2018) - [c37]Hamza Omar, Syed Kamran Haider, Ling Ren, Marten van Dijk, Omer Khan:
Breaking the Oblivious-RAM Bandwidth Wall. ICCD 2018: 115-122 - [c36]Halit Dogan, Masab Ahmad, José A. Joao, Omer Khan:
Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72. ICCD 2018: 496-505 - [c35]Masab Ahmad, Halit Dogan, Fabio Checconi, Xinyu Que, Daniele Buono, Omer Khan:
Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications. IPDPS 2018: 316-325 - 2017
- [j14]Masab Ahmad, Christopher J. Michael, Omer Khan:
Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs. IEEE Micro 37(1): 30-40 (2017) - [c34]Hamza Omar, Masab Ahmad, Omer Khan:
GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms. ICCD 2017: 201-208 - [c33]Halit Dogan, Farrukh Hijaz, Masab Ahmad, Brian Kahne, Peter Wilson, Omer Khan:
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging. IPDPS 2017: 254-264 - [i3]Qingchuan Shi, Hamza Omar, Omer Khan:
Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads. CoRR abs/1707.02589 (2017) - 2016
- [j13]Qingchuan Shi, George Kurian, Farrukh Hijaz
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies. ACM Trans. Archit. Code Optim. 13(4): 37:1-37:28 (2016) - [j12]Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan:
Locality-aware data replication in the last-level cache for large scale multicores. J. Supercomput. 72(2): 718-752 (2016) - [c32]Omer Khan, Maria K. Michael, Antonio Miele
Foreword. DFT 2016: iii - [c31]Masab Ahmad, Omer Khan:
GPU concurrency choices in graph analytics. IISWC 2016: 178-187 - [c30]Sandip Kundu, Omer Khan:
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. VLSID 2016: 12-13 - 2015
- [j11]Qingchuan Shi, Henry Hoffmann, Omer Khan:
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads. IEEE Comput. Archit. Lett. 14(2): 85-89 (2015) - [j10]Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas:
The Execution Migration Machine: Directoryless Shared-Memory Architecture. Computer 48(9): 50-59 (2015) - [c29]George Kurian, Qingchuan Shi, Srinivas Devadas, Omer Khan:
OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access. PACT 2015: 392-405 - [c28]Masab Ahmad, Kartik Lakshminarasimhan, Omer Khan:
Efficient parallelization of path planning workload on single-chip shared-memory multicores. HPEC 2015: 1-6 - [c27]Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk
M-MAP: Multi-factor memory authentication for secure embedded processors. ICCD 2015: 471-474 - [c26]Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan:
CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores. IISWC 2015: 44-55 - [c25]Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads. HASP@ISCA 2015: 6:1-6:8 - [c24]Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan:
Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication. NAS 2015: 122-129 - [i2]Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk:
M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors. IACR Cryptol. ePrint Arch. 2015: 831 (2015) - 2014
- [j9]Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas:
Thread Migration Prediction for Distributed Shared Caches. IEEE Comput. Archit. Lett. 13(1): 53-56 (2014) - [j8]Farrukh Hijaz, Omer Khan:
NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages. ACM Trans. Archit. Code Optim. 11(3): 29:1-29:28 (2014) - [c23]George Kurian, Srinivas Devadas, Omer Khan:
Locality-aware data replication in the Last-Level Cache. HPCA 2014: 1-12 - [c22]Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. HPCA 2014: 213-224 - [i1]Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk:
HaTCh: Hardware Trojan Catcher. IACR Cryptol. ePrint Arch. 2014: 943 (2014) - 2013
- [j7]Qingchuan Shi, Omer Khan:
Toward Holistic Soft-Error-Resilient Shared-Memory Multicores. Computer 46(10): 56-64 (2013) - [c21]Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas:
MARTHA: architecture for control and emulation of power electronics and smart grid systems. DATE 2013: 519-524 - [c20]Farrukh Hijaz, Qingchuan Shi, Omer Khan:
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages. ICCD 2013: 85-92 - [c19]Qingchuan Shi, Farrukh Hijaz, Omer Khan:
Towards efficient dynamic data placement in NoC-based multicores. ICCD 2013: 369-376 - [c18]George Kurian, Omer Khan, Srinivas Devadas:
The locality-aware adaptive cache coherence protocol. ISCA 2013: 523-534 - [c17]Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas:
A framework to accelerate sequential programs on homogeneous multicores. VLSI-SoC 2013: 344-347 - 2012
- [j6]Omer Khan, Sandip Kundu:
Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. IET Circuits Devices Syst. 6(5): 355-365 (2012) - [j5]Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas:
HORNET: A Cycle-Level Multicore Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 890-903 (2012) - [c16]Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas:
A low-overhead dynamic optimization framework for multicores. PACT 2012: 467-468 - [c15]Farrukh Hijaz, Qingchuan Shi, Omer Khan:
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores. MICRO Workshops 2012: 68-73 - 2011
- [j4]Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas:
DCC: A Dependable Cache Coherence Multicore Architecture. IEEE Comput. Archit. Lett. 10(1): 12-15 (2011) - [j3]Omer Khan, Sandip Kundu:
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Secur. Comput. 8(5): 714-727 (2011) - [j2]Omer Khan, Sandip Kundu:
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 84-110 (2011) - [c14]Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan:
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. PACT 2011: 121-130 - [c13]Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas:
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. ICCD 2011: 411-418 - [c12]Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas:
Scalable, accurate multicore simulation in the 1000-core era. ISPASS 2011: 175-185 - [c11]Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas:
Deadlock-free fine-grained thread migration. NOCS 2011: 33-40 - [c10]Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola L. Celanovic, Srinivas Devadas:
Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems. RTSS 2011: 305-316 - [c9]Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel A. Kinsy, Ilia A. Lebedev, Omer Khan, Srinivas Devadas:
Brief announcement: distributed shared memory based on computation migration. SPAA 2011: 253-256 - 2010
- [j1]Omer Khan, Sandip Kundu:
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers 59(5): 651-665 (2010) - [c8]Omer Khan, Sandip Kundu:
A model to exploit power-performance efficiency in superscalar processors via structure resizing. ACM Great Lakes Symposium on VLSI 2010: 215-220 - [c7]Omer Khan, Sandip Kundu:
A self-adaptive scheduler for asymmetric multi-cores. ACM Great Lakes Symposium on VLSI 2010: 397-400 - [c6]Rance Rodrigues, Sandip Kundu, Omer Khan:
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. ITC 2010: 219-228
2000 – 2009
- 2009
- [c5]Omer Khan, Sandip Kundu:
A self-adaptive system architecture to address transistor aging. DATE 2009: 81-86 - [c4]Abhisek Pan, Omer Khan, Sandip Kundu:
Improving yield and reliability of chip multiprocessors. DATE 2009: 490-495 - [c3]Omer Khan, Sandip Kundu:
Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE 2009: 952-957 - [c2]Omer Khan, Sandip Kundu:
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC 2009: 293-307 - 2008
- [c1]Omer Khan, Sandip Kundu:
A framework for predictive dynamic temperature management of microprocessor systems. ICCAD 2008: 258-263
Coauthor Index
Srini Devadas
aka: Srinivas Devadas
aka: Srinivas Devadas
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