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Michele Portolan
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2020 – today
- 2024
- [j6]Michele Portolan:
True Interactive Testing Based on IJTAG. IEEE Des. Test 41(6): 62-69 (2024) - [c39]Michele Portolan, Martin Keim, J. F. Coté, Hans-Martin Von Staud:
What Would Interactive Testing With 1687 Look Like? ETS 2024: 1 - 2023
- [j5]Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda:
Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4246-4259 (2023) - [c38]Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT 2023: 1-7 - [c37]Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg:
Refreshing the JTAG Family. VTS 2023: 1-7 - 2022
- [j4]Michele Portolan, Emanuele Valea, Paolo Maistri, Giorgio Di Natale:
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions. IEEE Des. Test 39(3): 117-124 (2022) - [c36]Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo:
IEEE P1687.1: Extending the Network Boundaries for Test. ITC 2022: 382-390 - [c35]Michele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos:
Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. ITC 2022: 539-543 - 2021
- [c34]Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim:
Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS 2021: 1-10 - [c33]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale:
Security EDA Extension through P1687.1 and 1687 Callbacks. ITC 2021: 344-353 - [c32]Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle:
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS 2021: 1-4 - 2020
- [j3]Michele Portolan:
Automated Testing Flow: The Present and the Future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2952-2963 (2020) - [c31]Michele Portolan, Jeff Rearick, Martin Keim:
Linking Chip, Board, and System Test via Standards. ETS 2020: 1-8 - [c30]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle:
Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS 2020: 1-6 - [c29]Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir:
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4 - [c28]Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
New Perspectives on Core In-field Path Delay Test. ITC 2020: 1-5 - [c27]Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick:
Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC 2020: 1-10
2010 – 2019
- 2019
- [c26]Michele Portolan, Riccardo Cantoro, Ernesto Sánchez:
A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. ETS 2019: 1-2 - [c25]Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale:
Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS 2019: 1-10 - [c24]Alessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo:
Approximate computing design exploration through data lifetime metrics. ETS 2019: 1-7 - [c23]Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov:
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. ITC 2019: 1-8 - 2017
- [c22]Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir:
Mixed-signal BIST computation offloading using IEEE 1687. ETS 2017: 1-2 - [c21]Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle:
Reliability of computing systems: From flip flops to variables. IOLTS 2017: 196-198 - 2016
- [c20]Michele Portolan:
A novel test generation and application flow for functional access to IEEE 1687 instruments. ETS 2016: 1-6 - [c19]Michele Portolan, Robin Rolland:
Student-driven development of a digital tester. EWME 2016: 1-3 - [c18]K. Chibani, Michele Portolan, Régis Leveugle:
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. IOLTS 2016: 54-59 - [c17]Michele Portolan:
Accessing 1687 systems using arbitrary protocols. ITC 2016: 1-9 - 2015
- [c16]Michele Portolan, K. Huang:
Special session 8C: E.J. McCluskey doctoral thesis award semi-final. VTS 2015: 1-2 - 2014
- [c15]K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle:
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS 2014: 778-781 - [c14]K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle:
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC 2014: 1-6 - [c13]Michele Portolan, Michail Maniatakos:
Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. VTS 2014: 1 - 2013
- [j2]Michele Portolan, Bradford G. Van Treuren, Suresh Goyal:
Executing IJTAG: Are Vectors Enough? IEEE Des. Test 30(5): 15-25 (2013) - [c12]Michele Portolan, Michail Maniatakos:
Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations. VTS 2013: 1 - [c11]Michele Portolan, Michail Maniatakos:
Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters. VTS 2013: 1 - [c10]Davide Cherubini, Michele Portolan:
Automatic equivalent model generation and evolution for small cell networks. WiOpt 2013: 62-67 - 2012
- [c9]Michele Portolan:
Packet-based JTAG for remote testing. ITC 2012: 1-6 - 2010
- [j1]Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook:
A Common Language Framework for Next-Generation Embedded Testing. IEEE Des. Test Comput. 27(5): 36-49 (2010) - [c8]Michele Portolan, Bradford G. Van Treuren, Suresh Goyal:
Scan chain securization though Open-Circuit Deadlocks. ITC 2010: 808
2000 – 2009
- 2009
- [c7]Michele Portolan, Suresh Goyal, Bradford G. Van Treuren:
Scalable and efficient integrated test architecture. ITC 2009: 1 - 2008
- [c6]Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche:
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS 2008: 113-116 - [c5]Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook:
A New Language Approach for IJTAG. ITC 2008: 1-10 - 2007
- [c4]Michele Portolan, Régis Leveugle:
Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT 2007: 370-378 - 2005
- [c3]Michele Portolan, Régis Leveugle:
Towards a Secure and Reliable System. EUC 2005: 1085-1098 - [c2]Michele Portolan, Régis Leveugle:
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS 2005: 247-252 - 2004
- [c1]Michele Portolan, Régis Leveugle:
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS 2004: 167-174
Coauthor Index
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last updated on 2024-11-11 22:26 CET by the dblp team
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