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Luigi Dilillo
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- affiliation: LIRMM Montpellier, France
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2020 – today
- 2023
- [j22]Annachiara Ruospo
, Ernesto Sánchez
A Survey on Deep Learning Resilience Assessment Methodologies. Computer 56(2): 57-66 (2023) - [c106]Wesley Grignani
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression. DFT 2023: 1-6 - [c105]Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo:
Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit. DFT 2023: 1-6 - [c104]Benjamin W. Mezger
Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip. DFT 2023: 1-6 - [c103]Douglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo:
Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments. DFT 2023: 1-6 - [c102]André Martins Pio de Mattos, Douglas A. dos Santos, Carolina Imianosky, Douglas R. Melo, Luigi Dilillo:
Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments. IWASI 2023: 227-232 - 2022
- [j21]Benjamin W. Mezger
A Survey of the RISC-V Architecture Software Support. IEEE Access 10: 51394-51411 (2022) - [j20]Lucas Matana Luza
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(4): 1867-1882 (2022) - [c101]Douglas A. dos Santos, André Martins Pio de Mattos
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. DFT 2022: 1-6 - [c100]Lucas Matana Luza, Frederic Wrobel
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. ETS 2022: 1-10 - 2021
- [c99]Lucas Matana Luza
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. DDECS 2021: 41-44 - [c98]Lucas Matana Luza
Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study. DTIS 2021: 1-6 - [c97]Douglas Rossi Melo
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. DTIS 2021: 1-6 - [c96]Douglas A. dos Santos
Characterization of a RISC-V System-on-Chip under Neutron Radiation. DTIS 2021: 1-6 - [c95]Annachiara Ruospo
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. LATS 2021: 1-5 - [e2]Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou:
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021. IEEE 2021, ISBN 978-1-6654-1609-2 [contents] - 2020
- [c94]Lucas Matana Luza
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT 2020: 1-6 - [c93]Lucas Matana Luza
Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS 2020: 1-6 - [c92]Douglas Almeida dos Santos, Lucas Matana Luza
A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. DTIS 2020: 1-5 - [e1]Luigi Dilillo, Mihalis Psarakis, Taniya Siddiqua:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, Frascati, Italy, October 19-21, 2020. IEEE 2020, ISBN 978-1-7281-9457-8 [contents]
2010 – 2019
- 2019
- [j19]Douglas R. Melo
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors 19(24): 5416 (2019) - [c91]Dario Asciolla, Luigi Dilillo, Douglas A. dos Santos, Douglas R. Melo
Characterization of a RISC-V Microcontroller Through Fault Injection. ApplePies 2019: 91-101 - [c90]Lucas Matana Luza
Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash Memory. DFT 2019: 1-6 - [c89]Iacopo Fara, Lucas Matana Luza
Design and Implementation of a Flexible Interface for TID Detector. IWASI 2019: 158-162 - [c88]Douglas Rossi de Melo
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. LATS 2019: 1-6 - [c87]Cezar Antônio Rigo
A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. LATS 2019: 1-6 - 2018
- [c86]Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo:
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS 2018: 1-5 - 2017
- [j18]Frederic Wrobel
A calculation method to estimate single event upset cross section. Microelectron. Reliab. 76-77: 644-649 (2017) - [c85]Marcelino Seif, Emna Farjallah, Franck Badets
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. ETS 2017: 1-6 - [c84]Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo:
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. ITC 2017: 1-9 - 2016
- [j17]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25(3): 1640013:1-1640013:18 (2016) - [c83]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED 2016: 185-191 - 2015
- [c82]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280 - [c81]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Design-for-Diagnosis Architecture for Power Switches. DDECS 2015: 43-48 - [c80]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6 - [c79]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Scan-chain intra-cell defects grading. DTIS 2015: 1-6 - [c78]Imran Wali, Arnaud Virazel
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c77]Anu Asokan, Alberto Bosio, Arnaud Virazel
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - [c76]Luigi Dilillo, Alexandre Bosser
Real-time SRAM based particle detector. IWASI 2015: 58-62 - 2014
- [j16]D. A. Tran, Arnaud Virazel
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j15]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [j14]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30(5): 611-627 (2014) - [j13]Aida Todri-Sanial
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [j12]Joao Azevedo, Arnaud Virazel
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2326-2335 (2014) - [c75]Yuanqing Cheng, Aida Todri-Sanial
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c74]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS 2014: 312-317 - [c73]Carolina Metzler, Aida Todri-Sanial
Timing-aware ATPG for critical paths with multiple TSVs. DDECS 2014: 116-121 - [c72]Anu Asokan, Aida Todri-Sanial
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c71]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
Test and diagnosis of power switches. DDECS 2014: 213-218 - [c70]Imran Wali, Arnaud Virazel
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - [c69]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
An intra-cell defect grading tool. DDECS 2014: 298-301 - [c68]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - [c67]Anu Asokan, Aida Todri-Sanial
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - [c66]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW 2014: 69-72 - [c65]Carolina Metzler, Aida Todri-Sanial
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS 2014: 1-6 - 2013
- [j11]Paolo Bernardi
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9(2): 253-263 (2013) - [j10]Aida Todri
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [j9]Aida Todri
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 958-970 (2013) - [c64]Elena I. Vatajelu
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - [c63]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 - [c62]Elena I. Vatajelu
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c61]Elena I. Vatajelu
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS 2013: 39-44 - [c60]Carolina Metzler, Aida Todri-Sanial
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c59]Elena I. Vatajelu
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS 2013: 1-6 - [c58]Georgios Tsiligiannis
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c57]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467 - [c56]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC 2013: 1-10 - [c55]Georgios Tsiligiannis
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c54]Aida Todri-Sanial
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS 2013: 1-4 - [c53]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS 2013: 1-6 - 2012
- [j8]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. J. Electron. Test. 28(2): 215-228 (2012) - [j7]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28(3): 317-329 (2012) - [c52]Joao Azevedo, Arnaud Virazel
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130 - [c51]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium 2012: 161-166 - [c50]Paolo Bernardi
Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium 2012: 167-172 - [c49]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium 2012: 221-226 - [c48]Joao Azevedo, Arnaud Virazel
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 - [c47]Joao Azevedo, Arnaud Virazel
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS 2012: 1 - [c46]Carolina Metzler, Aida Todri
Through-Silicon-Via resistive-open defect analysis. ETS 2012: 1 - [c45]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Defect analysis in power mode control logic of low-power SRAMs. ETS 2012: 1 - [c44]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122 - [c43]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10 - [c42]D. A. Tran, Arnaud Virazel
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 - [c41]Alberto Bosio, Luigi Dilillo, Patrick Girard
Advanced test methods for SRAMs. VTS 2012: 300-301 - 2011
- [c40]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c39]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c38]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 - [c37]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 - [c36]Aida Todri
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 - [c35]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 - [c34]Pierre-Didier Mauroux, Arnaud Virazel
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 - [c33]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 - [c32]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158 - [c31]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 - [c30]Luigi Dilillo, Paolo Rech
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW 2011: 1-6 - [c29]Jean-Marc Gallière, Luigi Dilillo:
Versatile march test generator for hands-on memory testing laboratory. MSE 2011: 41-42 - 2010
- [j6]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [c28]Paolo Rech
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 - [c27]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 - [c26]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 - [c25]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c24]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 - [c23]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. ETS 2010: 81-86 - [c22]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS 2010: 132-137 - [c21]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Setting test conditions for improving SRAM reliability. ETS 2010: 257 - [c20]Paolo Rech
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. IOLTS 2010: 29-34 - [c19]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805 - [c18]Jean-Marc Gallière, Paolo Rech
A roaming memory test bench for detecting particle induced SEUs. ITC 2010: 810 - [c17]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c16]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80
2000 – 2009
- 2009
- [c15]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 - [c14]Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348 - [c13]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 - [c12]Pierre-Didier Mauroux, Arnaud Virazel
NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 - 2008
- [c11]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 - 2007
- [j5]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. 23(5): 435-444 (2007) - [c10]Luigi Dilillo, Bashir M. Al-Hashimi:
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. DDECS 2007: 173-178 - 2006
- [j4]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. 22(3): 287-296 (2006) - [j3]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
Reducing Power Dissipation in SRAM during Test. J. Low Power Electron. 2(2): 271-280 (2006) - [c9]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
Minimizing test power in SRAM through reduction of pre-charge activity. DATE 2006: 1159-1164 - [c8]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 - 2005
- [j2]Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. 21(2): 169-179 (2005) - [j1]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. 21(5): 551-561 (2005) - [c7]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862 - [c6]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS 2005: 116-121 - [c5]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188 - 2004
- [c4]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271 - [c3]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS 2004: 140-145 - [c2]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138 - 2003
- [c1]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255
Coauthor Index
[j22] [j20] [c99] [c95] [c94] [c93] [j17] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j16] [j15] [j14] [j13] [j12] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [j11] [j10] [j9] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j8] [j7] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j6] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c19] [c17] [c16] [c15] [c13] [c12] [c11]
[j17] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j16] [j15] [j14] [j13] [j12] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [j11] [j10] [j9] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j8] [j7] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j6] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [j5] [j4] [j3] [c9] [c8] [j2] [j1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
Lucas M. Luza
aka: Lucas Matana Luza
aka: Lucas Matana Luza
Douglas A. dos Santos
aka: Douglas Almeida dos Santos
aka: Douglas Almeida dos Santos
Aida Todri
aka: Aida Todri-Sanial
aka: Aida Todri-Sanial
[j17] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [j16] [j15] [j14] [j13] [j12] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [j10] [j9] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [j8] [j7] [c52] [c51] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j6] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c19] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [j5] [j4] [c8] [j2] [j1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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