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TingTing Hwang
Tingting Hwang – Ting Ting Hwang
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2020 – today
- 2024
- [j48]Cheng-Hsien Lin
, Kuan-Ting Chen
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-27 (2024) - [c63]Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE 2024: 1-2 - 2023
- [c62]RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang:
Expanding In-Cone Obfuscated Tree for Anti SAT Attack. DATE 2023: 1-6 - [c61]Yuan-Tai Lin, Chin-Yu Sun, TingTing Hwang:
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties. SOCC 2023: 1-6 - 2021
- [j47]Chin-Yu Sun
A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. 94: 107325 (2021) - [j46]Chin-Yu Sun, Hsiao-Ling Wu, Hung-Min Sun, TingTing Hwang:
A New Attack for Self-Certified Digital Signatures for E-commerce Applications. J. Inf. Sci. Eng. 37(6): 1449-1466 (2021) - [c60]Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC 2021: 210-215
2010 – 2019
- 2019
- [c59]Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC 2019: 236-241 - [c58]Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang:
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC 2019: 400-405 - [i1]Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang:
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR abs/1908.07701 (2019) - 2017
- [j45]Yen-Hao Chen
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 820-832 (2017) - [c57]Chia-Ling Chen, Yen-Hao Chen, TingTing Hwang:
Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs. ASP-DAC 2017: 666-671 - [c56]Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang:
Architectural evaluations on TSV redundancy for reliability enhancement. DATE 2017: 566-571 - 2016
- [j44]Wei-Hen Lo
Architecture of Ring-Based Redundant TSV for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3437-3449 (2016) - [c55]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE 2016: 79-84 - [c54]Wei-Hen Lo, Kai-zen Liang, TingTing Hwang:
Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC). DATE 2016: 1084-1089 - 2015
- [c53]Wei-Hen Lo, Kang Chi, TingTing Hwang:
Architecture of ring-based redundant TSV for clustered faults. DATE 2015: 848-853 - 2014
- [j43]Fu-Wei Chen, TingTing Hwang:
Clock-Tree Synthesis with Methodology of Reuse in 3D-IC. ACM J. Emerg. Technol. Comput. Syst. 10(3): 22:1-22:22 (2014) - [j42]Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1031-1042 (2014) - [j41]Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang:
Utilizing Circuit Structure for Scan Chain Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2766-2778 (2014) - [c52]Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang:
Fault-tolerant TSV by using scan-chain test TSV. ASP-DAC 2014: 658-663 - [c51]Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang:
Compaction-free compressed cache for high performance multi-core system. ICCAD 2014: 140-147 - 2013
- [j40]Ang-Chih Hsieh, TingTing Hwang:
Thermal-aware memory mapping in 3D designs. ACM Trans. Embed. Comput. Syst. 13(1): 4:1-4:22 (2013) - [c50]Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking signal TSV for thermal dissipation in global routing for 3D IC. ASP-DAC 2013: 699-704 - [c49]Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang:
Utilizing circuit structure for scan chain diagnosis. ETS 2013: 1-6 - [c48]Po-Yang Hsu, TingTing Hwang:
Thread-criticality aware dynamic cache reconfiguration in multi-core system. ICCAD 2013: 413-420 - 2012
- [j39]Ang-Chih Hsieh, TingTing Hwang:
TSV Redundancy: Architecture and Design Issues in 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 711-722 (2012) - [j38]Ang-Chih Hsieh, TingTing Hwang:
Run-Time Reconfiguration of Expandable Cache for Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1863-1875 (2012) - [j37]Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2255-2264 (2012) - [c47]Fu-Wei Chen, TingTing Hwang:
Clock tree synthesis with methodology of re-use in 3D IC. DAC 2012: 1094-1099 - 2011
- [j36]Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang:
Through-Silicon Via Planning in 3-D Floorplanning. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1448-1457 (2011) - [c46]Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang:
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. ASP-DAC 2011: 231-236 - [c45]Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
A physical-location-aware fault redistribution for maximum IR-drop reduction. ASP-DAC 2011: 701-706 - [c44]Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang:
A new architecture for power network in 3D IC. DATE 2011: 401-406 - [c43]Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang:
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. ICPP 2011: 552-561 - 2010
- [j35]Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin:
A Fast Digital Chaotic Generator for Secure Communication. Int. J. Bifurc. Chaos 20(12): 3969-3987 (2010) - [j34]Wen-Wen Hsieh, Shih-Liang Chen, I-Sheng Lin, TingTing Hwang:
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 289-298 (2010) - [j33]Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin:
Randomness Enhancement Using Digitalized Modified Logistic Map. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 996-1000 (2010) - [j32]Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang:
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1686-1695 (2010) - [c42]Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
TSV redundancy: Architecture and design issues in 3D IC. DATE 2010: 166-171
2000 – 2009
- 2009
- [j31]Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2): 31:1-31:17 (2009) - [j30]Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma:
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ACM Trans. Design Autom. Electr. Syst. 14(4): 53:1-53:22 (2009) - [c41]Wen-Wen Hsieh, TingTing Hwang:
Thermal-aware post compilation for VLIW architectures. ASP-DAC 2009: 606-611 - [c40]Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang:
New spare cell design for IR drop minimization in Engineering Change Order. DAC 2009: 402-407 - [c39]Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang:
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. DATE 2009: 1234-1237 - [c38]Ang-Chih Hsieh, TingTing Hwang:
Thermal-aware memory mapping in 3D designs. DATE 2009: 1361-1366 - 2008
- [j29]Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang:
Digital Secure-Communication Using Robust Hyper-Chaotic Systems. Int. J. Bifurc. Chaos 18(11): 3325-3339 (2008) - [j28]Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang:
Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): 14:1-14:14 (2008) - [c37]Po-Yuan Chen, Che-Yu Liu, TingTing Hwang:
Transition-aware decoupling-capacitor allocation in power noise reduction. ICCAD 2008: 426-429 - 2007
- [j27]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 564-573 (2007) - [j26]Yi-Yu Liu, TingTing Hwang:
Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1155-1161 (2007) - [j25]Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang:
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2222-2227 (2007) - [j24]Yung-Chia Lin, Yi-Ping You
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. J. Supercomput. 42(2): 201-223 (2007) - [j23]Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang:
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. ACM Trans. Design Autom. Electr. Syst. 12(3): 30:1-30:25 (2007) - [c36]Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379 - 2006
- [j22]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006) - [j21]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang:
Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006) - [j20]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 81-85 (2006) - [j19]Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang:
Instruction buffering for nested loops in low-power design. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 780-784 (2006) - [c35]Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang:
Switching-activity driven gate sizing and Vth assignment for low power design. ASP-DAC 2006: 576-581 - [c34]Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang:
A bus architecture for crosstalk elimination in high performance processor design. CODES+ISSS 2006: 247-252 - [c33]Yi-Yu Liu, TingTing Hwang:
Crosstalk-aware domino logic synthesis. DATE 2006: 1312-1317 - [c32]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006 - 2005
- [c31]Yi-Ping You
Low-power techniques for network security processors. ASP-DAC 2005: 355-360 - [c30]Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu:
Functionality directed clustering for low power MTCMOS design. ASP-DAC 2005: 862-867 - [c29]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314 - 2004
- [c28]Yen-Te Ho, TingTing Hwang:
Low power design using dual threshold voltage. ASP-DAC 2004: 205-208 - [c27]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665 - [c26]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang:
Crosstalk Minimization in Logic Synthesis for PLA. DATE 2004: 790-795 - [c25]Chi-Wei Hu, TingTing Hwang:
Output-pattern directed decomposition for low power design. ISCAS (5) 2004: 137-140 - [c24]Yung-Chia Lin, Yi-Ping You
Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC 2004: 470-484 - 2003
- [j18]Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai:
Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Design Autom. Electr. Syst. 8(2): 252-268 (2003) - [c23]Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103 - [c22]Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135 - [c21]MingHung Lee, TingTing Hwang, Shi-Yu Huang:
Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153 - 2002
- [j17]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) - [c20]Shih-Liang Chen, TingTing Hwang, C. L. Liu:
A technology mapping algorithm for CPLD architectures. FPT 2002: 204-210 - [c19]Chi Ta Wu, TingTing Hwang:
Instruction buffering for nested loops in low power design. ISCAS (4) 2002: 81-84 - 2001
- [j16]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 383-389 (2001) - [c18]LiYi Lin, Yi-Yu Liu, TingTing Hwang:
A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC 2001: 126-132 - [c17]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu:
Binary decision diagram with minimum expected path length. DATE 2001: 708-712 - 2000
- [c16]Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai:
Compiler Optimization on Instruction Scheduling for Low Power. ISSS 2000: 55-61
1990 – 1999
- 1999
- [j15]How-Rern Lin, TingTing Hwang:
On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 231-238 (1999) - [c15]Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang:
A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. ASP-DAC 1999: 77-80 - [c14]Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu:
Logic Transformation for Low Power Synthesis. DATE 1999: 158-162 - 1998
- [j14]Chau-Shen Chen, TingTing Hwang:
Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electron. Test. 13(1): 19-27 (1998) - [c13]Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang:
A Re-engineering Approach to Low Power FPGA Design Using SPFD. DAC 1998: 722-725 - [c12]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. ICCAD 1998: 408-411 - 1997
- [j13]Kuo-Hua Wang, TingTing Hwang:
Boolean matching for incompletely specified functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2): 160-168 (1997) - [j12]Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang:
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 316-320 (1997) - [c11]Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661 - 1996
- [j11]How-Rern Lin, Yu-Chin Hsu, TingTing Hwang:
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31(5): 668-676 (1996) - [j10]Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1226-1236 (1996) - [j9]Kuo-Hua Wang, TingTing Hwang, Cheng Chen:
Exploiting communication complexity for Boolean matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1249-1256 (1996) - [j8]Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu:
Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996) - [c10]Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang:
Layout Driven Selecting and Chaining of Partial Scan. DAC 1996: 262-267 - 1995
- [j7]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995) - [c9]How-Rern Lin, TingTing Hwang:
Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995 - [c8]Kuo-Hua Wang, TingTing Hwang:
Boolean Matching for Incompletely Specified Functions. DAC 1995: 48-53 - 1994
- [j6]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 137-149 (1994) - [j5]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang:
Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1280-1287 (1994) - [j4]Kuo-Hua Wang, Cheng Chen, Ting Ting Hwang:
Technology Mapping for FPGA Using Generalized Functional Decomposition. VLSI Design 2(2): 89-103 (1994) - [c7]How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang:
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429 - [c6]How-Rern Lin, TingTing Hwang:
Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484 - [c5]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
State Assignment for Power and Area Minimization. ICCD 1994: 250-254 - 1993
- [c4]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127 - 1992
- [j3]Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang:
ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41(9): 1181-1184 (1992) - [j2]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 545-554 (1992) - [c3]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. EURO-DAC 1992: 118-123 - 1990
- [j1]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1017-1027 (1990) - [c2]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Logic synthesis for programmable logic devices. ICCD 1990: 364-367
1980 – 1989
- 1989
- [c1]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Multi-Level Logic Synthesis Using Communication Complexity. DAC 1989: 215-220
Coauthor Index
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