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Low-power techniques for network security processors

Authors:

Sheng-Yu HsuAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 355 - 360

https://doi.org/10.1145/1120725.1120869

Published: 18 January 2005 Publication History

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Abstract

In this paper, we present several techniques for low-power design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

References

[1]

C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A high-throughput low-cost AES processor," IEEE Communications Magazine, vol. 41, no. 12, pp. 86-91, Dec. 2003.

Digital Library

Google Scholar

[2]

J.-H. Hong and C.-W. Wu, "Cellular array modular multiplier for the RSA public-key cryptosystem based on modified Booth's algorithm," IEEE Transactions on VLSI Systems, vol. 11, no. 3, pp. 474-484, June 2003.

Digital Library

Google Scholar

[3]

S. Devadas and S. Malik, "A survey of optimization techniques targeting low power VLSI circuits," In Proceedings of the 32nd ACM/IEEE Conference on Design Automation, pp. 242-247, 1995.

Digital Library

Google Scholar

[4]

Y.-C. Lin, Y.-P. You, C.-W. Huang, J. K. Lee, W.-K. Shih, and T.T. Hwang, "Power-aware scheduling for parallel security processors with analytical models," Submitted to The 17th International Workshop on Languages and Compilers for Parallel Computing, 2004.

Digital Library

Google Scholar

[5]

C. L. Liu and J. W. Layland, "Scheduling algorithms for multi-programming in a hard read-time environment," Journal of the ACM, 20(1):46-61, 1973.

Digital Library

Google Scholar

[6]

A. Stratakos, S. Sanders, and R. Brodersen, "A low-voltage CMOS DCDC converter for a portable battery-operated system," In Proceedings of IEEE Power Electronics Specialists Conference, pp. 619-626, 1994.

Google Scholar

[7]

S. Borkar, "Low power challenges for the decade," In Proceedings of ASP-DAC, 2001.

Digital Library

Google Scholar

[8]

J. Kao, S. Narendra and A. Chandrakasan "Subthreshold leakage modeling and reduction techniques," In Proceddings of ICCAD, pp. 141-148, 2002.

Digital Library

Google Scholar

[9]

Y.-T. Ho, T.T. Hwang, "Low power design using dual threshold voltage," In Proceedings of ASP-DAC, pp. 205-208,2004.

Digital Library

Google Scholar

[10]

C. Chen, X. Yang and M. Sarrafzadeh, "Potential slack: an effective metric of combinational circuit performance," In Proceedings of ICCAD, pp.198-201, 2000.

Digital Library

Google Scholar

Cited By

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Tseng CHuang P(2007)A 100¿A Digital Controller with Transient Enhancement for Dynamic Voltage Output Switching-type DC-DC Converter2007 IEEE Symposium on VLSI Circuits10.1109/VLSIC.2007.4342751(24-25)Online publication date: Jun-2007
https://doi.org/10.1109/VLSIC.2007.4342751

Low-power techniques for network security processors
1. Hardware

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Information

Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

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ASPDAC05

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SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Tseng CHuang P(2007)A 100¿A Digital Controller with Transient Enhancement for Dynamic Voltage Output Switching-type DC-DC Converter2007 IEEE Symposium on VLSI Circuits10.1109/VLSIC.2007.4342751(24-25)Online publication date: Jun-2007
https://doi.org/10.1109/VLSIC.2007.4342751

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Power-aware compilation techniques for high performance processors

Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts

Performance evaluation and low power design of network processors